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m3: changed clk 0 1 2 to 100MHz (#636)

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* m3: changed clk 0 1 2 to 100MHz

* m3:fix clk 2

* binaries in
This commit is contained in:
Dhanya Thattil
2023-01-25 11:54:37 +01:00
committed by GitHub
parent c7af9c9f3e
commit 3f7c9529dd
3 changed files with 4 additions and 4 deletions
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BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv7.0.0.rc2
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6
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -57,9 +57,9 @@
#define DEFAULT_TRIMBIT_VALUE (0)
#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
#define DEFAULT_READOUT_C0 (12) //(083333333) // rdo_clk, 83.33 MHz
#define DEFAULT_READOUT_C1 (12) //(083333333) // rdo_smp_clk, 83.33 MHz
#define DEFAULT_SYSTEM_C0 (20) //(050000000) // run_clk, 20 MHz
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // rdo_smp_clk, 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (8) //(125000000) // str_clk, 125 MHz const
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz