mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-21 11:20:04 +02:00
added registers_m.h
git-svn-id: file:///afs/psi.ch/project/sls_det_software/svn/slsDetectorSoftware@558 951219d9-93cf-4727-9268-0efd64621fa3
This commit is contained in:
l_maliakal_d
parent
5b30a98b47
commit
3e32d977b4
@ -637,14 +637,14 @@ int getThresholdEnergy() {
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if (myg>0 && myo>0) {
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//ethr=(myo-detectorDacs[VTHRESH+imod*NDAC])*1000/myg;
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ethr=(myo-setDACRegister(VREF_DS,-1,imod))*1000/myg;//edited by dhanya
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ethr=(myo-setDACRegister(VDAC0,-1,imod))*1000/myg;//edited by dhanya
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// else
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// ethr=-1;
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}
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#ifdef VERBOSE
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//printf("module=%d gain=%f, offset=%f, dacu=%f\n",imod, myg, myo, detectorDacs[VTHRESH+imod*NDAC]);
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printf("module=%d gain=%f, offset=%f, dacu=%d\n",imod, myg, myo,(int)(setDACRegister(VREF_DS,-1,imod)));//edited by dhanya
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printf("module=%d gain=%f, offset=%f, dacu=%d\n",imod, myg, myo,(int)(setDACRegister(VDAC0,-1,imod)));//edited by dhanya
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printf("Threshold energy of module %d is %d eV\n", imod, ethr);
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#endif
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@ -709,7 +709,7 @@ int setThresholdEnergy(int ethr) {
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printf("could not set threshold energy for module %d, settings %d (offset is %f; gain is %f)\n",imod,thisSettings,myo,myg);
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#endif
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}
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initDACbyIndexDACU(VREF_DS, dacu, imod); ///needs to be fixed dhanya
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initDACbyIndexDACU(VDAC0, dacu, imod); ///needs to be fixed dhanya
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}
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return ret;
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}
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@ -1559,25 +1559,25 @@ int initModulebyNumber(sls_detector_module myMod) {
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*/
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v[VREF_DS]=(myMod.dacs)[0];
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v[VCASCN_PB]=(myMod.dacs)[1];
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v[VCASCP_PB]=(myMod.dacs)[2];
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v[VOUT_CM]=(myMod.dacs)[3];
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v[VCASC_OUT]=(myMod.dacs)[4];
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v[VIN_CM]=(myMod.dacs)[5];
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v[VREF_COMP]=(myMod.dacs)[6];
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v[IB_TESTC]=(myMod.dacs)[7];
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v[VDAC0]=(myMod.dacs)[0];
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v[VDAC1]=(myMod.dacs)[1];
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v[VDAC2]=(myMod.dacs)[2];
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v[VDAC3]=(myMod.dacs)[3];
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v[VDAC4]=(myMod.dacs)[4];
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v[VDAC5]=(myMod.dacs)[5];
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v[VDAC6]=(myMod.dacs)[6];
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v[VDAC7]=(myMod.dacs)[7];
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#ifdef VERBOSE
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printf("imod=%d\n",imod);
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printf("vrefds=%d\n",v[VREF_DS]);
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printf("vcascn=%d\n",v[VCASCN_PB]);
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printf("vcascp=%d\n",v[VCASCP_PB]);
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printf("vout=%d\n",v[VOUT_CM]);
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printf("vcasc=%d\n",v[VCASC_OUT]);
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printf("vin=%d\n",v[VIN_CM]);
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printf("vref_comp=%d\n",v[VREF_COMP]);
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printf("ib_testc=%d\n",v[IB_TESTC]);
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printf("vdac0=%d\n",v[VDAC0]);
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printf("vdac1=%d\n",v[VDAC1]);
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printf("vdac2=%d\n",v[VDAC2]);
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printf("vdac3=%d\n",v[VDAC3]);
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printf("vdac4=%d\n",v[VDAC4]);
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printf("vdac5=%d\n",v[VDAC5]);
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printf("vdac6=%d\n",v[VDAC6]);
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printf("vdac7=%d\n",v[VDAC7]);
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#endif
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@ -17,7 +17,7 @@
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#define DEFAULTOFFSET {817.5,828.6,804.2}
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// DAC definitions
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enum dacsVal{VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN_CM, VREF_COMP, IB_TESTC,HIGH_VOLTAGE, CONFGAIN};
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enum dacsVal{VDAC0, VDAC1, VDAC2, VDAC3, VDAC4, VDAC5, VDAC6, VDAC7, HIGH_VOLTAGE, CONFGAIN};
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/* DAC adresses */
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#define DACCS {0,0,1,1,2,2,3,3,4,4,5,5,6,6}
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297
slsDetectorSoftware/moenchDetectorServer/registers_m.h
Executable file
297
slsDetectorSoftware/moenchDetectorServer/registers_m.h
Executable file
@ -0,0 +1,297 @@
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#ifndef REGISTERS_G_H
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#define REGISTERS_G_H
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#include "sls_detector_defs.h"
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/* Definitions for FPGA*/
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#define CSP0 0x20200000
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#define MEM_SIZE 0x100000
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/* values defined for FPGA */
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#define MCSNUM 0x0
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#define FIXED_PATT_VAL 0xacdc1980
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#define FPGA_INIT_PAT 0x60008
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#define FPGA_INIT_ADDR 0xb0000000
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/* registers defined in FPGA */
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#define PCB_REV_REG 0x2c<<11
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#define GAIN_REG 0x10<<11
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//#define FLOW_CONTROL_REG 0x11<<11
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//#define FLOW_STATUS_REG 0x12<<11
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//#define FRAME_REG 0x13<<11
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#define MULTI_PURPOSE_REG 0x14<<11
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#define DAQ_REG 0x15<<11
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//#define TIME_FROM_START_REG 0x16<<11
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#define MCB_CNTRL_REG_OFF 0x17<<11// control the dacs
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//ADC
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#define ADC_WRITE_REG 0x18<<11
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#define ADC_SYNC_REG 0x19<<11
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//#define MUTIME_REG 0x1a<<11
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//temperature
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#define TEMP_IN_REG 0x1b<<11
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#define TEMP_OUT_REG 0x1c<<11
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//configure MAC
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#define TSE_CONF_REG 0x1d<<11
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#define ENET_CONF_REG 0x1e<<11
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//#define WRTSE_SHAD_REG 0x1f<<11
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//HV
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#define HV_REG 0x20<<11
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#define DUMMY_REG 0x21<<11
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#define FPGA_VERSION_REG 0x22<<11
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#define FIX_PATT_REG 0x23<<11
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#define CONTROL_REG 0x24<<11
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#define STATUS_REG 0x25<<11
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#define CONFIG_REG 0x26<<11
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#define EXT_SIGNAL_REG 0x27<<11
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#define FPGA_SVN_REG 0x29<<11
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#define CHIP_OF_INTRST_REG 0x2A<<11
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//FIFO
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#define LOOK_AT_ME_REG 0x28<<11
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#define FIFO_DATA_REG_OFF 0x50<<11 ///////
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//to read back dac registers
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#define MOD_DACS1_REG 0x65<<11
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#define MOD_DACS2_REG 0x66<<11
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#define MOD_DACS3_REG 0x67<<11
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//user entered
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#define SET_DELAY_LSB_REG 0x68<<11
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#define SET_DELAY_MSB_REG 0x69<<11
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#define GET_DELAY_LSB_REG 0x6a<<11
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#define GET_DELAY_MSB_REG 0x6b<<11
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#define SET_TRAINS_LSB_REG 0x6c<<11
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#define SET_TRAINS_MSB_REG 0x6d<<11
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#define GET_TRAINS_LSB_REG 0x6e<<11
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#define GET_TRAINS_MSB_REG 0x6f<<11
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#define SET_FRAMES_LSB_REG 0x70<<11
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#define SET_FRAMES_MSB_REG 0x71<<11
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#define GET_FRAMES_LSB_REG 0x72<<11
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#define GET_FRAMES_MSB_REG 0x73<<11
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#define SET_PERIOD_LSB_REG 0x74<<11
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#define SET_PERIOD_MSB_REG 0x75<<11
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#define GET_PERIOD_LSB_REG 0x76<<11
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#define GET_PERIOD_MSB_REG 0x77<<11
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#define SET_EXPTIME_LSB_REG 0x78<<11
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#define SET_EXPTIME_MSB_REG 0x79<<11
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#define GET_EXPTIME_LSB_REG 0x7a<<11
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#define GET_EXPTIME_MSB_REG 0x7b<<11
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#define SET_GATES_LSB_REG 0x7c<<11
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#define SET_GATES_MSB_REG 0x7d<<11
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#define GET_GATES_LSB_REG 0x7e<<11
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#define GET_GATES_MSB_REG 0x7f<<11
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//image
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#define DARK_IMAGE_REG 0x81<<11
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#define GAIN_IMAGE_REG 0x82<<11
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//counter block memory
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#define COUNTER_MEMORY_REG 0x85<<11
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#define GET_MEASUREMENT_TIME_LSB_REG 0x023000
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#define GET_MEASUREMENT_TIME_MSB_REG 0x024000
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#define GET_ACTUAL_TIME_LSB_REG 0x025000
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#define GET_ACTUAL_TIME_MSB_REG 0x026000
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//not used
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//#define MCB_DOUT_REG_OFF 0x200000
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//#define FIFO_CNTRL_REG_OFF 0x300000
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//#define FIFO_COUNTR_REG_OFF 0x400000
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//not used so far
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//#define SPEED_REG 0x006000
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//#define SET_NBITS_REG 0x008000
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//not used
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//#define GET_SHIFT_IN_REG 0x022000
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#define SHIFTMOD 2
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#define SHIFTFIFO 9
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/** for PCB_REV_REG */
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#define DETECTOR_TYPE_MASK 0xF0000
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#define DETECTOR_TYPE_OFFSET 16
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#define BOARD_REVISION_MASK 0xFFFF
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#define MOENCH_MODULE 2
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/* for control register */
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#define START_ACQ_BIT 0x00000001
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#define STOP_ACQ_BIT 0x00000002
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#define START_FIFOTEST_BIT 0x00000004 // ?????
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#define STOP_FIFOTEST_BIT 0x00000008 // ??????
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#define START_READOUT_BIT 0x00000010
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#define STOP_READOUT_BIT 0x00000020
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#define START_EXPOSURE_BIT 0x00000040
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#define STOP_EXPOSURE_BIT 0x00000080
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#define START_TRAIN_BIT 0x00000100
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#define STOP_TRAIN_BIT 0x00000200
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#define SYNC_RESET 0x00000400
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/* for status register */
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#define RUN_BUSY_BIT 0x00000001
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#define READOUT_BUSY_BIT 0x00000002
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#define FIFOTEST_BUSY_BIT 0x00000004 //????
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#define WAITING_FOR_TRIGGER_BIT 0x00000008
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#define DELAYBEFORE_BIT 0x00000010
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#define DELAYAFTER_BIT 0x00000020
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#define EXPOSING_BIT 0x00000040
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#define COUNT_ENABLE_BIT 0x00000080
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#define READSTATE_0_BIT 0x00000100
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#define READSTATE_1_BIT 0x00000200
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#define READSTATE_2_BIT 0x00000400
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#define RUNSTATE_0_BIT 0x00001000
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#define RUNSTATE_1_BIT 0x00002000
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#define RUNSTATE_2_BIT 0x00004000
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#define SOME_FIFO_FULL_BIT 0x00008000 // error!
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#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
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#define RUNMACHINE_BUSY_BIT 0x00020000
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#define READMACHINE_BUSY_BIT 0x00040000
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/* for fifo status register */
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#define FIFO_ENABLED_BIT 0x80000000
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#define FIFO_DISABLED_BIT 0x01000000
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#define FIFO_ERROR_BIT 0x08000000
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#define FIFO_EMPTY_BIT 0x04000000
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#define FIFO_DATA_READY_BIT 0x02000000
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#define FIFO_COUNTER_MASK 0x000001ff
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#define FIFO_NM_MASK 0x00e00000
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#define FIFO_NM_OFF 21
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#define FIFO_NC_MASK 0x001ffe00
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#define FIFO_NC_OFF 9
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/* for config register *///not really used yet
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#define TOT_ENABLE_BIT 0x00000002
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#define TIMED_GATE_BIT 0x00000004
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#define CONT_RO_ENABLE_BIT 0x00080000
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#define CPU_OR_RECEIVER_BIT 0x00001000
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/* for speed register */
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#define CLK_DIVIDER_MASK 0x000000ff
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#define CLK_DIVIDER_OFFSET 0
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#define SET_LENGTH_MASK 0x00000f00
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#define SET_LENGTH_OFFSET 8
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#define WAIT_STATES_MASK 0x0000f000
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#define WAIT_STATES_OFFSET 12
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#define TOTCLK_DIVIDER_MASK 0xff000000
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#define TOTCLK_DIVIDER_OFFSET 24
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#define TOTCLK_DUTYCYCLE_MASK 0x00ff0000
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#define TOTCLK_DUTYCYCLE_OFFSET 16
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/* for external signal register */
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#define SIGNAL_OFFSET 4
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#define SIGNAL_MASK 0xF
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#define EXT_SIG_OFF 0x0
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#define EXT_GATE_IN_ACTIVEHIGH 0x1
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#define EXT_GATE_IN_ACTIVELOW 0x2
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#define EXT_TRIG_IN_RISING 0x3
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#define EXT_TRIG_IN_FALLING 0x4
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#define EXT_RO_TRIG_IN_RISING 0x5
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#define EXT_RO_TRIG_IN_FALLING 0x6
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#define EXT_GATE_OUT_ACTIVEHIGH 0x7
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#define EXT_GATE_OUT_ACTIVELOW 0x8
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#define EXT_TRIG_OUT_RISING 0x9
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#define EXT_TRIG_OUT_FALLING 0xA
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#define EXT_RO_TRIG_OUT_RISING 0xB
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#define EXT_RO_TRIG_OUT_FALLING 0xC
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/* for temperature register */
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#define T1_CLK_BIT 0x00000001
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#define T1_CS_BIT 0x00000002
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#define T2_CLK_BIT 0x00000004
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#define T2_CS_BIT 0x00000008
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/* fifo control register */
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#define FIFO_RESET_BIT 0x00000001
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#define FIFO_DISABLE_TOGGLE_BIT 0x00000002
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//chip shiftin register meaning
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#define OUTMUX_OFF 20
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#define OUTMUX_MASK 0x1f
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#define PROBES_OFF 4
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#define PROBES_MASK 0x7f
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#define OUTBUF_OFF 0
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#define OUTBUF_MASK 1
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/* multi purpose register */
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#define PHASE_STEP_BIT 0x00000001
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#define PHASE_STEP_OFFSET 0
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// #define xxx_BIT 0x00000002
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#define RESET_COUNTER_BIT 0x00000004
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#define RESET_COUNTER_OFFSET 2
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//#define xxx_BIT 0x00000008
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//#define xxx_BIT 0x00000010
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#define SW1_BIT 0x00000020
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#define SW1_OFFSET 5
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#define WRITE_BACK_BIT 0x00000040
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#define WRITE_BACK_OFFSET 6
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#define RESET_BIT 0x00000080
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#define RESET_OFFSET 7
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#define ENET_RESETN_BIT 0x00000800
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#define ENET_RESETN_OFFSET 11
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#define INT_RSTN_BIT 0x00002000
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#define INT_RSTN_OFFSET 13
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#define DIGITAL_TEST_BIT 0x00004000
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#define DIGITAL_TEST_OFFSET 14
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//#define CHANGE_AT_POWER_ON_BIT 0x00008000
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//#define CHANGE_AT_POWER_ON_OFFSET 15
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/* settings/conf gain register */
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#define GAIN_MASK 0x0000000f
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#define GAIN_OFFSET 0
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#define SETTINGS_MASK 0x000000f0
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#define SETTINGS_OFFSET 4
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/* CHIP_OF_INTRST_REG */
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#define CHANNEL_MASK 0xffff0000
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#define CHANNEL_OFFSET 16
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#define ACTIVE_ADC_MASK 0x0000001f
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/**ADC SYNC CLEAN FIFO*/
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#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
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#define CLEAN_FIFO_MASK 0x0fffff
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#endif
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@ -939,37 +939,37 @@ int set_dac(int file_des) {
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#ifdef MCB_FUNCS
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switch (ind) {
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case G_VREF_DS :
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idac=VREF_DS;
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case V_DAC0 :
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idac=VDAC0;
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break;
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case G_VCASCN_PB:
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idac=VCASCN_PB;
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case V_DAC1:
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idac=VDAC1;
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break;
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case G_VCASCP_PB:
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idac=VCASCP_PB;
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case V_DAC2:
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idac=VDAC2;
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break;
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case G_VOUT_CM:
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idac=VOUT_CM;
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case V_DAC3:
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idac=VDAC3;
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break;
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case G_VCASC_OUT:
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idac=VCASC_OUT;
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case V_DAC4:
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idac=VDAC4;
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break;
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case G_VIN_CM:
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idac=VIN_CM;
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case V_DAC5:
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idac=VDAC5;
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break;
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case G_VREF_COMP:
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idac=VREF_COMP;
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case V_DAC6:
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idac=VDAC6;
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break;
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case G_IB_TESTC:
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idac=IB_TESTC;
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case V_DAC7:
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idac=VDAC7;
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break;
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case HV_POT:
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idac=HIGH_VOLTAGE;
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break;
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default:
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printf("Unknown DAC index %d\n",ind);
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sprintf(mess,"Unknown DAC index %d\n",ind);
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printf("Unknown DAC index %d for Moench\n",ind);
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sprintf(mess,"Unknown DAC index %d for Moench\n",ind);
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ret=FAIL;
|
||||
break;
|
||||
}
|
||||
|
||||
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Reference in New Issue
Block a user