Dev/define cmd (#1312)

* basic ctb config api for register and bit names

* tests for define and definelist pass. yet to implement using them for reg, setbit, clearbit and getbit

* improved autocomplete for getbit,setbit, clearbit

* validate autocomplete

* definelist has no put

* updating help

* converting char array+int in runtimeerror compiles but throws at runtime.Fixed.Tested for it. Also check if string or int before using getregisterdefinitonbyvalue to see if it threw to call the other function. because both of it can throw and we should differentiate the issues for both

* removed std::vector<std::pair<string,int> to std::map<string, int> for defiitions list

* Dev/define cmd tie bit to reg (#1328)

* strong type

* moved everythign to bit_utils class

* pybindings

* added tests for python

* removed duplicates

* removed bit names in reg

* changed BitPosition to BitAddress

* Using define reg/bit from python (#1344)

* define_bit, define_addr in python. 
* setBit/clearBit takes int or addr

* added example using bits

* split define into 2 commands define_reg and define_bit, definelist into 2: definelist_reg and definelist_bit

* allow string for register and bit names in c++ api

* refactor from github comments

* naming refactoring (getRegisterDefnition to retunr name and address specifically

* added marker for 8 cmd tests connected to define, changed macro to static constexpr

* changed bitPosition from int to uint32_t

* got rid of setbitposition and setaddress, instead overloaded constructor to take in strings so that the conversion from string to bit address members, takes place within the class for easy maintainance in case type changes

* Removing implicit conversions:
RegisterAddresss and RegisterValue: Removed the implicit conversions.
RegisterAddress: Changed member name from address_ to value_ and method as well to value().
RegisterValue: Also added | operator to be able to concatenate with uint32_t. Same in python bindings (but could not find the tests to modify

* Allowed concatenation with other RegisterValue, made them all constexpr

* fix a ctbConfig test

* Maponstack works with integration tests, but need unit tests

* tests on mapstack

* fixed ctb tests and FixedString being initialized with gibberish

* removing parsing from string inside the class RegisterAddress, BitAddress and RegisterValue

* updated python bindings

* fixed bit utils test

* renaming getRegisterDefintiionAddress/Name=>getRegisterAddress/Name and similary for getBitDefinitionAddress/Name

* updated python bindings

* fix tests (format)

* a few python tests added and python bindings corrected

* replaceing str with __str__ for bit.cpp

* repr reimplemented for bit.cpp

* removed make with registerAddress etc

* starting server for tests per session and nor module

* killprocess throws if no process found-> github runs fails, changed to pkill and not throw

* clean shm shouldnt raise, in ci binary not found

* ignoring these tests for CI, which fail on CI because simulators are not generated in CI. This is in another PR, where it should work

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>

python/slsdet/detector.py

@@ -3,6 +3,7 @@
 from ._slsdet import CppDetectorApi
 from ._slsdet import slsDetectorDefs
 from ._slsdet import IpAddr, MacAddr
+from ._slsdet import RegisterAddress, RegisterValue, BitAddress
 
 runStatus = slsDetectorDefs.runStatus
 timingMode = slsDetectorDefs.timingMode
@@ -1813,6 +1814,148 @@ class Detector(CppDetectorApi):
         [Eiger] Address is +0x100 for only left, +0x200 for only right.
         """
         return self._register
+    
+    def define_reg(self, *, name: str, addr):
+        """
+        [Ctb] Define a name for a register to be used later with reg.
+
+        Example
+        --------
+
+        d.define_reg('myreg',addr=0x6)
+        d.define_reg('myreg',addr=RegisterAddress(0x6))')
+        """
+        if isinstance(addr, int):
+            addr = RegisterAddress(addr)
+        elif not isinstance(addr, RegisterAddress):
+            raise ValueError("addr must int or RegisterAddress")
+        self.setRegisterDefinition(name, addr)
+
+
+    def define_bit(self, *, name: str, addr, bit_position:int=None):
+        """
+        [Ctb] Define a name for a bit in a register to be used later with setBit/clearBit/getBit
+
+        Example
+        --------
+
+        bit1 = BitAddress(RegisterAddress(0x6),7)
+        d.define_bit('mybit',addr=bit1)
+        d.define_bit('mybit',addr=0x6, bit=7)
+        d.define_bit('mybit',addr=RegisterAddress(0x6), bit=7)
+        d.define_bit('mybit',addr='myreg', bit=7) #if myreg defined before
+        """
+
+        # bitAddress
+        if isinstance(addr, BitAddress):
+            if bit_position is not None:
+                raise ValueError("If addr is BitAddress, bit_position must be None")
+            bitaddr = addr
+        # register name/address + bit_position
+        else:
+            if isinstance(addr, str):
+                addr = self.getRegisterAddress(addr)
+            elif isinstance(addr, int):
+                addr = RegisterAddress(addr)
+            elif not isinstance(addr, RegisterAddress):
+                raise ValueError("addr must be str, int or RegisterAddress")
+            
+            if bit_position is None:
+                raise ValueError("bit_position must be provided if addr is used.")
+            if not isinstance(bit_position, int):
+                raise ValueError("bit_position must be int")
+
+            bitaddr = BitAddress(addr, bit_position)
+
+        self.setBitDefinition(name, bitaddr)
+
+    def _resolve_bit_name_or_addr(self, bitname_or_addr, bit_position=None):
+        """
+        Internal function to resolve bit name or address arguments for setBit, clearBit and getBit
+        Returns a BitAddress
+        """
+        #Old usage passing two ints  or [RegisterAddress and int]
+        if isinstance(bitname_or_addr, (int, RegisterAddress)):
+            if bit_position is None:
+                raise ValueError("bit_position must be provided when passing int address")
+            if not isinstance(bit_position, int):
+                raise ValueError("bit_position must be int")
+            return BitAddress(bitname_or_addr, bit_position)
+
+        # New usage with str or BitAddress
+        # str
+        if isinstance(bitname_or_addr, str):
+            bitname_or_addr = self.getBitAddress(bitname_or_addr)
+
+        if bit_position is not None:
+            raise ValueError("bit_position must be None when passing str or BitAddress")
+
+        #must now be a BitAddress
+        if not isinstance(bitname_or_addr, BitAddress):
+            raise ValueError("bitname_or_addr must be str, BitAddress, int or RegisterAddress")
+
+        return bitname_or_addr
+        
+
+    def setBit(self, bitname_or_addr, bit_position=None):
+        """
+        Set a bit in a register
+        [Ctb] Can use a named bit address
+
+        Example
+        --------
+        d.setBit(0x5, 3)
+        d.setBit(RegisterAddress(0x5), 3)
+        
+        #Ctb
+        d.setBit('mybit')
+
+        myreg = RegisterAddress(0x5)
+        mybit = BitAddress(myreg, 5) 
+        d.setBit(mybit)
+        """
+        resolved = self._resolve_bit_name_or_addr(bitname_or_addr, bit_position)
+        return super().setBit(resolved)
+        
+    def clearBit(self, bitname_or_addr, bit_position=None):
+        """
+        Clear a bit in a register
+        [Ctb] Can use a named bit address
+
+        Example
+        --------
+        d.clearBit(0x5, 3)
+        
+        #Ctb
+        d.clearBit('mybit')
+
+        myreg = RegisterAddress(0x5)
+        mybit = BitAddress(myreg, 5) 
+        d.clearBit(mybit)
+        """
+        resolved = self._resolve_bit_name_or_addr(bitname_or_addr, bit_position)
+        return super().clearBit(resolved)
+
+    @element
+    def getBit(self, bitname_or_addr, bit_position=None):
+        """
+        Get a bit from a register
+        [Ctb] Can use a named bit address
+
+        Example
+        --------
+        d.getBit(0x5, 3)
+        
+        #Ctb
+        d.getBit('mybit')
+
+        myreg = RegisterAddress(0x5)
+        mybit = BitAddress(myreg, 5) 
+        d.getBit(mybit)
+        """
+        resolved = self._resolve_bit_name_or_addr(bitname_or_addr, bit_position)
+        return super().getBit(resolved)  
+
 
     @property
     def slowadc(self):