mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-22 09:37:59 +02:00
merge conflict removed, jungfrau server and eiger server re compiled
This commit is contained in:
@ -62,6 +62,14 @@
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||||
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST) //Not used in software
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||||
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/* API Version Register */
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#define API_VERSION_REG (0x0F << 11)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
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/* Time from Start 64 bit register */
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#define TIME_FROM_START_LSB_REG (0x10 << 11)
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#define TIME_FROM_START_MSB_REG (0x11 << 11)
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@ -188,7 +196,7 @@
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#define CONFIG_TDMA_ENABLE_VAL ((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
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#define CONFIG_TDMA_TIMESLOT_OFST (25)
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#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
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#define CONFIG_TDMA_TIMESLOT_0_VAL ((0x0 << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)
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/* External Signal Register */
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#define EXT_SIGNAL_REG (0x4E << 11)
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@ -211,6 +219,8 @@
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#define CONTROL_DDR3_MEM_RST_MSK (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) //only PHY, not DDR3 PLL ,Not used in software
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#define CONTROL_ACQ_FIFO_CLR_OFST (14)
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#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
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#define CONTROL_STORAGE_CELL_NUM_OFST (16)
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#define CONTROL_STORAGE_CELL_NUM_MSK (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
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/* Reconfiguratble PLL Paramater Register */
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#define PLL_PARAM_REG (0x50 << 11)
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@ -278,7 +288,13 @@
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#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
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/** Vref Comp Mod Register */
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#define VREF_COMP_MOD_REG (0x5C << 11) //Not used in software, TBD in firmware
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#define VREF_COMP_MOD_REG (0x5C << 11)
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#define VREF_COMP_MOD_OFST (0)
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#define VREF_COMP_MOD_MSK (0x00000FFF << VREF_COMP_MOD_OFST)
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#define VREF_COMP_MOD_ENABLE_OFST (31)
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#define VREF_COMP_MOD_ENABLE_MSK (0x00000FFF << VREF_COMP_MOD_ENABLE_OFST)
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/** DAQ Register */
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#define DAQ_REG (0x5D << 11) //TBD in firmware
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@ -288,6 +304,21 @@
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#define CHIP_POWER_ENABLE_OFST (0)
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#define CHIP_POWER_ENABLE_MSK (0x00000001 << CHIP_POWER_ENABLE_OFST)
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#define CHIP_POWER_STATUS_OFST (1)
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#define CHIP_POWER_STATUS_MSK (0x00000001 << CHIP_POWER_STATUS_OFST)
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/** Temperature Control Register */
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#define TEMP_CTRL_REG (0x5F << 11)
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#define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
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#define TEMP_CTRL_PROTCT_THRSHLD_MSK (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
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#define TEMP_CTRL_PROTCT_ENABLE_OFST (16)
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#define TEMP_CTRL_PROTCT_ENABLE_MSK (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
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#define TEMP_CTRL_OVR_TMP_EVNT_OFST (31)
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#define TEMP_CTRL_OVR_TMP_EVNT_MSK (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
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#define TEMP_CTRL_CLR_OVR_TMP_EVNT_VAL ((0x1 << TEMP_CTRL_OVR_TMP_EVNT_OFST) & TEMP_CTRL_OVR_TMP_EVNT_MSK)
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/* Set Delay 64 bit register */
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#define SET_DELAY_LSB_REG (0x60 << 11)
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@ -309,6 +340,10 @@
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#define SET_EXPTIME_LSB_REG (0x68 << 11)
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#define SET_EXPTIME_MSB_REG (0x69 << 11)
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/* Trigger Delay 32 bit register */
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#define SET_TRIGGER_DELAY_LSB_REG (0x70 << 11)
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#define SET_TRIGGER_DELAY_MSB_REG (0x71 << 11)
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/* Module Coordinates Register 0 */
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#define COORD_0 (0x7C << 11)
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@ -323,6 +358,14 @@
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#define COORD_0_Z_OFST (0)
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#define COORD_0_Z_MSK (0x0000FFFF << COORD_0_Z_OFST)
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/* ASIC Control Register */
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#define ASIC_CTRL_REG (0x7F)
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#define ASIC_CTRL_PRCHRG_TMR_OFST (0)
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#define ASIC_CTRL_PRCHRG_TMR_MSK (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
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#define ASIC_CTRL_DS_TMR_OFST (8)
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#define ASIC_CTRL_DS_TMR_MSK (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
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#endif //REGISTERS_G_H
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BIN
slsDetectorSoftware/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
Executable file
BIN
slsDetectorSoftware/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
Executable file
Binary file not shown.
@ -1,9 +1,9 @@
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||||
Path: slsDetectorsPackage/slsDetectorSoftware/jungfrauDetectorServer
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||||
URL: origin git@git.psi.ch:sls_detectors_software/slsDetectorPackage.git
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Repository Root: origin git@git.psi.ch:sls_detectors_software/slsDetectorPackage.git
|
||||
Repsitory UUID: 2f3dc8d109de8607f3217cf429619073dc9cc60e
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||||
Revision: 103
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URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
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Repsitory UUID: 08fda2b6620353e69f4b654f8bf4c3ea4be60b1e
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||||
Revision: 105
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Branch: developer
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Last Changed Author: Dhanya_Maliakal
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Last Changed Rev: 3397
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Last Changed Date: 2017-12-04 18:23:05.000000002 +0100 ./RegisterDefs.h
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Last Changed Rev: 3582
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Last Changed Date: 2018-02-05 11:53:33.000000002 +0100 ./RegisterDefs.h
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@ -1,6 +1,6 @@
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||||
#define GITURL "git@git.psi.ch:sls_detectors_software/slsDetectorPackage.git"
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||||
#define GITREPUUID "2f3dc8d109de8607f3217cf429619073dc9cc60e"
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||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
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||||
#define GITREPUUID "08fda2b6620353e69f4b654f8bf4c3ea4be60b1e"
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||||
#define GITAUTH "Dhanya_Maliakal"
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||||
#define GITREV 0x3397
|
||||
#define GITDATE 0x20171204
|
||||
#define GITREV 0x3582
|
||||
#define GITDATE 0x20180205
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#define GITBRANCH "developer"
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||||
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@ -29,12 +29,12 @@ void checkFirmwareCompatibility(int flag) {
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defineGPIOpins();
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resetFPGA();
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if (mapCSP0() == FAIL) {
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cprintf(BG_RED, "Dangerous to continue. Goodbye!\n");
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exit(EXIT_FAILURE);
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}
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if (mapCSP0() == FAIL) {
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cprintf(BG_RED, "Dangerous to continue. Goodbye!\n");
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exit(EXIT_FAILURE);
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}
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// does check only if flag is 0 (by default), set by command line
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// does check only if flag is 0 (by default), set by command line
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if ((!flag) && ((checkType() == FAIL) || (testFpga() == FAIL) || (testBus() == FAIL))) {
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cprintf(BG_RED, "Dangerous to continue. Goodbye!\n");
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exit(EXIT_FAILURE);
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@ -46,7 +46,9 @@ void checkFirmwareCompatibility(int flag) {
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uint64_t macadd = getDetectorMAC();
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int64_t fwversion = getDetectorId(DETECTOR_FIRMWARE_VERSION);
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int64_t swversion = getDetectorId(DETECTOR_SOFTWARE_VERSION);
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//int64_t sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
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int64_t sw_fw_apiversion = 0;
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if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
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sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
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cprintf(BLUE,"\n\n"
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"********************************************************\n"
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"****************** Jungfrau Server *********************\n"
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@ -55,46 +57,49 @@ void checkFirmwareCompatibility(int flag) {
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"Hardware Serial Nr:\t\t 0x%x\n"
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"Detector IP Addr:\t\t 0x%x\n"
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"Detector MAC Addr:\t\t 0x%llx\n"
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"Detector MAC Addr:\t\t 0x%llx\n\n"
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"Firmware Version:\t\t 0x%llx\n"
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"Software Version:\t\t 0x%llx\n"
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//"F/w-S/w API Version:\t\t 0x%llx\n"
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//"Required Firmware Version:\t 0x%x\n"
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"F/w-S/w API Version:\t\t 0x%llx\n"
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"Required Firmware Version:\t 0x%x\n"
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"\n"
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"********************************************************\n",
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hversion, hsnumber,
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ipadd, macadd,
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fwversion, swversion
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//, sw_fw_apiversion, REQUIRED_FIRMWARE_VERSION
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fwversion, swversion,
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sw_fw_apiversion, REQRD_FRMWR_VRSN
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);
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// return if flag is not zero, debug mode
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if (flag)
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return;
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/*
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* printf("Testing firmware capability... ");
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//cant read versions
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printf("Testing Firmware-software compatibility ...\n");
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if(!fwversion || !sw_fw_apiversion){
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cprintf(RED,"FATAL ERROR: Cant read versions from FPGA. Please update firmware\n");
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cprintf(RED,"Exiting Server. Goodbye!\n\n");
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exit(-1);
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exit(EXIT_FAILURE);
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}
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//check for API compatibility - old server
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if(sw_fw_apiversion > REQUIRED_FIRMWARE_VERSION){
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if(sw_fw_apiversion > REQRD_FRMWR_VRSN){
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cprintf(RED,"FATAL ERROR: This software version is incompatible.\n"
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"Please update it to be compatible with this firmware\n\n");
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cprintf(RED,"Exiting Server. Goodbye!\n\n");
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exit(-1);
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exit(EXIT_FAILURE);
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}
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//check for firmware compatibility - old firmware
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if( REQUIRED_FIRMWARE_VERSION > fwversion){
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if( REQRD_FRMWR_VRSN > fwversion){
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cprintf(RED,"FATAL ERROR: This firmware version is incompatible.\n"
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"Please update it to v%d to be compatible with this server\n\n", REQUIRED_FIRMWARE_VERSION);
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"Please update it to v%d to be compatible with this server\n\n", REQRD_FRMWR_VRSN);
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cprintf(RED,"Exiting Server. Goodbye!\n\n");
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exit(-1);
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exit(EXIT_FAILURE);
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}
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*/
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printf("Compatibility - success\n");
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}
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@ -176,28 +181,26 @@ int64_t getDetectorId(enum idMode arg){
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||||
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switch(arg){
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case DETECTOR_SERIAL_NUMBER:
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retval = getDetectorNumber();// or getDetectorMAC()
|
||||
break;
|
||||
return getDetectorNumber();// or getDetectorMAC()
|
||||
case DETECTOR_FIRMWARE_VERSION:
|
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retval = getFirmwareVersion();
|
||||
break;
|
||||
//case SOFTWARE_FIRMWARE_API_VERSION:
|
||||
//return GetFirmwareSoftwareAPIVersion();
|
||||
return getFirmwareVersion();
|
||||
case SOFTWARE_FIRMWARE_API_VERSION:
|
||||
return getFirmwareAPIVersion();
|
||||
case DETECTOR_SOFTWARE_VERSION:
|
||||
retval= GITREV;
|
||||
retval= (retval <<32) | GITDATE;
|
||||
break;
|
||||
return (GITDATE & 0xFFFFFF);
|
||||
default:
|
||||
break;
|
||||
return retval;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
u_int64_t getFirmwareVersion() {
|
||||
return ((bus_r(FPGA_VERSION_REG) & BOARD_REVISION_MSK) >> BOARD_REVISION_OFST);
|
||||
}
|
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|
||||
u_int64_t getFirmwareAPIVersion() {
|
||||
return ((bus_r(API_VERSION_REG) & API_VERSION_MSK) >> API_VERSION_OFST);
|
||||
}
|
||||
|
||||
u_int16_t getHardwareVersionNumber() {
|
||||
return ((bus_r(MOD_SERIAL_NUM_REG) & HARDWARE_VERSION_NUM_MSK) >> HARDWARE_VERSION_NUM_OFST);
|
||||
}
|
||||
@ -260,7 +263,7 @@ u_int32_t getDetectorIP(){
|
||||
/* initialization */
|
||||
|
||||
void initControlServer(){
|
||||
clkPhase[0] = 0; clkPhase[1] = 0;
|
||||
clkPhase[0] = 0; clkPhase[1] = 0;
|
||||
setupDetector();
|
||||
printf("\n");
|
||||
}
|
||||
@ -359,6 +362,12 @@ void setupDetector() {
|
||||
/*setSpeed(CLOCK_DIVIDER, HALF_SPEED); depends if all the previous stuff works*/
|
||||
setTiming(DEFAULT_TIMING_MODE);
|
||||
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
|
||||
|
||||
/* temporary set up until new firmware fixes bug */
|
||||
// set temperature threshold
|
||||
setThresholdTemperature(DEFAULT_TMP_THRSHLD);
|
||||
// reset temp event
|
||||
setTemperatureEvent(0);
|
||||
}
|
||||
|
||||
|
||||
@ -380,9 +389,30 @@ int powerChip (int on){
|
||||
bus_w(CHIP_POWER_REG, bus_r(CHIP_POWER_REG) & ~CHIP_POWER_ENABLE_MSK);
|
||||
}
|
||||
}
|
||||
return bus_r(CHIP_POWER_REG);
|
||||
|
||||
return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_ENABLE_MSK) >> CHIP_POWER_ENABLE_OFST);
|
||||
/* temporary setup until new firmware fixes bug */
|
||||
//return ((bus_r(CHIP_POWER_REG) & CHIP_POWER_STATUS_MSK) >> CHIP_POWER_STATUS_OFST);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int autoCompDisable(int on) {
|
||||
if(on != -1){
|
||||
if(on){
|
||||
cprintf(BLUE, "\n*** Auto comp disable mode: enabling ***\n");
|
||||
bus_w(VREF_COMP_MOD_REG, bus_r(VREF_COMP_MOD_REG) | VREF_COMP_MOD_ENABLE_MSK);
|
||||
}
|
||||
else{
|
||||
cprintf(BLUE, "\n*** Auto comp disable mode: disabling *** \n");
|
||||
bus_w(VREF_COMP_MOD_REG, bus_r(VREF_COMP_MOD_REG) & ~VREF_COMP_MOD_ENABLE_MSK);
|
||||
}
|
||||
}
|
||||
|
||||
return (bus_r(VREF_COMP_MOD_REG) & VREF_COMP_MOD_ENABLE_MSK);
|
||||
}
|
||||
|
||||
|
||||
void cleanFifos() {
|
||||
printf("\nClearing Acquisition Fifos\n");
|
||||
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_ACQ_FIFO_CLR_MSK);
|
||||
@ -455,33 +485,65 @@ int setSpeed(enum speedVariable arg, int val) {
|
||||
// setting
|
||||
if(val >= 0) {
|
||||
|
||||
switch(val){
|
||||
// stop state machine if running
|
||||
if(runBusy())
|
||||
stopStateMachine();
|
||||
|
||||
// stop state machine if running
|
||||
if(runBusy())
|
||||
stopStateMachine();
|
||||
uint32_t txndelay_msk = 0;
|
||||
|
||||
switch(val){
|
||||
|
||||
// todo in firmware, for now setting half speed
|
||||
case FULL_SPEED://40
|
||||
printf("\nSetting Half Speed (20 MHz):\n");
|
||||
printf("Setting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED); bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
|
||||
printf("Setting Config Reg to 0x%x\n", CONFIG_HALF_SPEED); bus_w(CONFIG_REG, CONFIG_HALF_SPEED);
|
||||
printf("Setting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL); bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
|
||||
printf("Setting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED); adcPhase(ADC_PHASE_HALF_SPEED);
|
||||
|
||||
printf("Setting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED);
|
||||
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
|
||||
|
||||
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
|
||||
printf("Setting Config Reg to 0x%x\n", CONFIG_HALF_SPEED | txndelay_msk);
|
||||
bus_w(CONFIG_REG, CONFIG_HALF_SPEED | txndelay_msk);
|
||||
|
||||
printf("Setting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL);
|
||||
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
|
||||
|
||||
printf("Setting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED);
|
||||
adcPhase(ADC_PHASE_HALF_SPEED);
|
||||
|
||||
break;
|
||||
case HALF_SPEED:
|
||||
printf("\nSetting Half Speed (20 MHz):\n");
|
||||
printf("Setting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED); bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
|
||||
printf("Setting Config Reg to 0x%x\n", CONFIG_HALF_SPEED); bus_w(CONFIG_REG, CONFIG_HALF_SPEED);
|
||||
printf("Setting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL); bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
|
||||
printf("Setting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED); adcPhase(ADC_PHASE_HALF_SPEED);
|
||||
|
||||
printf("Setting Sample Reg to 0x%x\n", SAMPLE_ADC_HALF_SPEED);
|
||||
bus_w(SAMPLE_REG, SAMPLE_ADC_HALF_SPEED);
|
||||
|
||||
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
|
||||
printf("Setting Config Reg to 0x%x\n", CONFIG_HALF_SPEED | txndelay_msk);
|
||||
bus_w(CONFIG_REG, CONFIG_HALF_SPEED | txndelay_msk);
|
||||
|
||||
printf("Setting ADC Ofst Reg to 0x%x\n", ADC_OFST_HALF_SPEED_VAL);
|
||||
bus_w(ADC_OFST_REG, ADC_OFST_HALF_SPEED_VAL);
|
||||
|
||||
printf("Setting ADC Phase Reg to 0x%x\n", ADC_PHASE_HALF_SPEED);
|
||||
adcPhase(ADC_PHASE_HALF_SPEED);
|
||||
|
||||
break;
|
||||
case QUARTER_SPEED:
|
||||
printf("\nSetting Half Speed (10 MHz):\n");
|
||||
printf("Setting Sample Reg to 0x%x\n", SAMPLE_ADC_QUARTER_SPEED); bus_w(SAMPLE_REG, SAMPLE_ADC_QUARTER_SPEED);
|
||||
printf("Setting Config Reg to 0x%x\n", CONFIG_QUARTER_SPEED); bus_w(CONFIG_REG, CONFIG_QUARTER_SPEED);
|
||||
printf("Setting ADC Ofst Reg to 0x%x\n", ADC_OFST_QUARTER_SPEED_VAL); bus_w(ADC_OFST_REG, ADC_OFST_QUARTER_SPEED_VAL);
|
||||
printf("Setting ADC Phase Reg to 0x%x\n", ADC_PHASE_QUARTER_SPEED); adcPhase(ADC_PHASE_QUARTER_SPEED);
|
||||
|
||||
printf("Setting Sample Reg to 0x%x\n", SAMPLE_ADC_QUARTER_SPEED);
|
||||
bus_w(SAMPLE_REG, SAMPLE_ADC_QUARTER_SPEED);
|
||||
|
||||
txndelay_msk = (bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK); // read config tdma timeslot value
|
||||
printf("Setting Config Reg to 0x%x\n", CONFIG_QUARTER_SPEED | txndelay_msk);
|
||||
bus_w(CONFIG_REG, CONFIG_QUARTER_SPEED | txndelay_msk);
|
||||
|
||||
printf("Setting ADC Ofst Reg to 0x%x\n", ADC_OFST_QUARTER_SPEED_VAL);
|
||||
bus_w(ADC_OFST_REG, ADC_OFST_QUARTER_SPEED_VAL);
|
||||
|
||||
printf("Setting ADC Phase Reg to 0x%x\n", ADC_PHASE_QUARTER_SPEED);
|
||||
adcPhase(ADC_PHASE_QUARTER_SPEED);
|
||||
|
||||
break;
|
||||
}
|
||||
printf("\n");
|
||||
@ -543,7 +605,7 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
|
||||
printf("\nSetting delay to %lldns\n", (long long int)val);
|
||||
val *= (1E-3 * CLK_SYNC);
|
||||
}
|
||||
retval = set64BitReg(val, SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-3 * CLK_SYNC);
|
||||
retval = set64BitReg(val, SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-3 * CLK_SYNC);
|
||||
printf("Getting delay: %lldns\n", (long long int)retval);
|
||||
break;
|
||||
|
||||
@ -835,6 +897,11 @@ void setDAC(enum DACINDEX ind, int val, int imod, int mV, int retval[]){
|
||||
DAC_SERIAL_CLK_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_MSK, DAC_SERIAL_DIGITAL_OUT_OFST);
|
||||
|
||||
dacValues[ind] = dacval;
|
||||
|
||||
if (ind == VREF_COMP) {
|
||||
bus_w (VREF_COMP_MOD_REG, (bus_r(VREF_COMP_MOD_REG) &~ (VREF_COMP_MOD_MSK)) // reset
|
||||
| ((val << VREF_COMP_MOD_OFST) & VREF_COMP_MOD_MSK)); // or it with value
|
||||
}
|
||||
}
|
||||
|
||||
printf("Getting DAC %d : ",ind);
|
||||
@ -1129,6 +1196,82 @@ void configurePll() {
|
||||
|
||||
|
||||
|
||||
int setThresholdTemperature(int val) {
|
||||
|
||||
if (val >= 0) {
|
||||
printf("\nThreshold Temperature: %d\n", val);
|
||||
|
||||
val *= (10.0/625.0);
|
||||
#ifdef VERBOSE
|
||||
printf("Converted Threshold Temperature: %d\n", val);
|
||||
#endif
|
||||
bus_w(TEMP_CTRL_REG, (bus_r(TEMP_CTRL_REG) &~(TEMP_CTRL_PROTCT_THRSHLD_MSK) &~(TEMP_CTRL_OVR_TMP_EVNT_MSK))
|
||||
| (((val << TEMP_CTRL_PROTCT_THRSHLD_OFST) & TEMP_CTRL_PROTCT_THRSHLD_MSK)));
|
||||
#ifdef VERBOSE
|
||||
printf("Converted Threshold Temperature set to %d\n", ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_PROTCT_THRSHLD_MSK) >> TEMP_CTRL_PROTCT_THRSHLD_OFST));
|
||||
#endif
|
||||
}
|
||||
uint32_t temp = ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_PROTCT_THRSHLD_MSK) >> TEMP_CTRL_PROTCT_THRSHLD_OFST);
|
||||
|
||||
// conversion
|
||||
temp *= (625.0/10.0);
|
||||
printf("Threshold Temperature %f °C\n",(double)temp/1000.00);
|
||||
|
||||
return temp;
|
||||
|
||||
}
|
||||
|
||||
|
||||
int setTemperatureControl(int val) {
|
||||
if (val >= 0) {
|
||||
// binary value
|
||||
if (val > 0 ) val = 1;
|
||||
printf("\nTemperature control: %d\n", val);
|
||||
bus_w(TEMP_CTRL_REG, (bus_r(TEMP_CTRL_REG) &~(TEMP_CTRL_PROTCT_ENABLE_MSK) &~(TEMP_CTRL_OVR_TMP_EVNT_MSK))
|
||||
| (((val << TEMP_CTRL_PROTCT_ENABLE_OFST) & TEMP_CTRL_PROTCT_ENABLE_MSK)));
|
||||
#ifdef VERBOSE
|
||||
printf("Temperature control set to %d\n", ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_PROTCT_ENABLE_MSK) >> TEMP_CTRL_PROTCT_ENABLE_OFST));
|
||||
#endif
|
||||
}
|
||||
return ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_PROTCT_ENABLE_MSK) >> TEMP_CTRL_PROTCT_ENABLE_OFST);
|
||||
}
|
||||
|
||||
|
||||
int setTemperatureEvent(int val) {
|
||||
if (val >= 0) {
|
||||
// set bit to clear it
|
||||
val = 1;
|
||||
printf("\nTemperature Event: %d\n", val);
|
||||
bus_w(TEMP_CTRL_REG, (bus_r(TEMP_CTRL_REG) &~TEMP_CTRL_OVR_TMP_EVNT_MSK)
|
||||
| (((val << TEMP_CTRL_OVR_TMP_EVNT_OFST) & TEMP_CTRL_OVR_TMP_EVNT_MSK)));
|
||||
#ifdef VERBOSE
|
||||
printf("Temperature Event set to %d\n", ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_OVR_TMP_EVNT_MSK) >> TEMP_CTRL_OVR_TMP_EVNT_OFST));
|
||||
#endif
|
||||
}
|
||||
return ((bus_r(TEMP_CTRL_REG) & TEMP_CTRL_OVR_TMP_EVNT_MSK) >> TEMP_CTRL_OVR_TMP_EVNT_OFST);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int setNetworkParameter(enum NETWORKINDEX mode, int value) {
|
||||
if (mode != TXN_FRAME)
|
||||
return -1;
|
||||
|
||||
if (value >= 0) {
|
||||
printf("\nSetting transmission delay: %d\n", value);
|
||||
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) &~CONFIG_TDMA_TIMESLOT_MSK)
|
||||
| (((value << CONFIG_TDMA_TIMESLOT_OFST) & CONFIG_TDMA_TIMESLOT_MSK)));
|
||||
#ifdef VERBOSE
|
||||
printf("Transmission delay set to %d\n", ((bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK) >> CONFIG_TDMA_TIMESLOT_OFST));
|
||||
#endif
|
||||
}
|
||||
|
||||
return ((bus_r(CONFIG_REG) & CONFIG_TDMA_TIMESLOT_MSK) >> CONFIG_TDMA_TIMESLOT_OFST);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* aquisition */
|
||||
|
||||
|
||||
@ -8,7 +8,8 @@
|
||||
|
||||
|
||||
#define GOODBYE (-200)
|
||||
//#define REQUIRED_FIRMWARE_VERSION 16
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x171113
|
||||
#define REQRD_FRMWR_VRSN 0x171113
|
||||
|
||||
|
||||
/* Struct Definitions */
|
||||
@ -48,13 +49,14 @@ enum DACINDEX {VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF
|
||||
0x1f00, /* FORCESWITCHG1 */ \
|
||||
0x3f00 /* FORCESWITCHG2 */ \
|
||||
};
|
||||
#define DEFAULT_SETT_NAMES { "Dynamic Gain", /* DYNAMICGAIN */ \
|
||||
#define DEFAULT_SETT_NAMES { "Dynamic Gain", /* DYNAMICGAIN */ \
|
||||
"Dynamic High Gain 0", /* DYNAMICHG0 */ \
|
||||
"Fix Gain 1", /* FIXGAIN1 */ \
|
||||
"Fix Gain 2", /* FIXGAIN2 */ \
|
||||
"Force Switch Gain 1", /* FORCESWITCHG1*/ \
|
||||
"Force Switch Gain 2" /* FORCESWITCHG2*/ \
|
||||
};
|
||||
};
|
||||
enum NETWORKINDEX { TXN_FRAME };
|
||||
|
||||
|
||||
|
||||
@ -84,16 +86,19 @@ enum DACINDEX {VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
#define DEFAULT_TMP_THRSHLD (65*1000) //milli degree Celsius
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define FIX_PATT_VAL (0xACDC2014)
|
||||
#define ADC_PORT_INVERT_VAL (0x453b2a9c)
|
||||
#define MAX_TIMESLOT_VAL (0x1F)
|
||||
#define MAX_THRESHOLD_TEMP_VAL (127999) //millidegrees
|
||||
|
||||
|
||||
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x1000 */
|
||||
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x2810 */
|
||||
#define CONFIG_HALF_SPEED (CONFIG_TDMA_TIMESLOT_0_VAL + CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_TIMESLOT_0_VAL + CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define CONFIG_HALF_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
|
||||
#define ADC_OFST_HALF_SPEED_VAL (0x20) //adc pipeline
|
||||
#define ADC_OFST_QUARTER_SPEED_VAL (0x0f)
|
||||
#define ADC_PHASE_HALF_SPEED (0x41)
|
||||
|
||||
Reference in New Issue
Block a user