Dev/xilinx acq (#901)

* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx

tests/scripts/test_simulators.py

@@ -99,9 +99,7 @@ def loadConfig(name, rx_hostname, settingsdir):
     Log(Fore.GREEN, 'Loading config')
     try:
         d = Detector()
-        if name == 'xilinx_ctb':
-            d.hostname = 'localhost'
-        elif name == 'eiger':
+        if name == 'eiger':
             d.hostname = 'localhost:' + str(DEFAULT_TCP_CNTRL_PORTNO) + '+localhost:' + str(HALFMOD2_TCP_CNTRL_PORTNO)
             #d.udp_dstport = {2: 50003} 
             # will set up for every module
@@ -120,8 +118,10 @@ def loadConfig(name, rx_hostname, settingsdir):
                 d.udp_srcip = d.udp_dstip
             else:
                 d.udp_srcip = 'auto'
-        if d.type == detectorType.JUNGFRAU or d.type == detectorType.MOENCH:
+        if d.type == detectorType.JUNGFRAU or d.type == detectorType.MOENCH or d.type == detectorType.XILINX_CHIPTESTBOARD:
             d.powerchip = 1
+        if d.type == detectorType.XILINX_CHIPTESTBOARD:
+            d.configureTransceiver()
     except:
         Log(Fore.RED, 'Could not load config for ' + name)
         raise
@@ -221,7 +221,7 @@ with open(fname, 'w') as fp:
             startCmdTests(server, fp, file_results)
             cleanup(server)
         except:
-            Log(log.RED, 'Exception caught. Cleaning up.')
+            Log(Fore.RED, 'Exception caught. Cleaning up.')
             cleanup(server)
             sys.stdout = original_stdout
             sys.stderr = original_stderr