Dev/xilinx acq (#901)

* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx

slsReceiverSoftware/src/MasterAttributes.h

@@ -152,6 +152,12 @@ class MasterAttributes {
 #ifdef HDF5C
     void WriteCtbHDF5Attributes(H5::H5File *fd, H5::Group *group);
 #endif
+
+    void GetXilinxCtbBinaryAttributes(
+        rapidjson::PrettyWriter<rapidjson::StringBuffer> *w);
+#ifdef HDF5C
+    void WriteXilinxCtbHDF5Attributes(H5::H5File *fd, H5::Group *group);
+#endif
 };
 
 } // namespace sls