detectors/slsDetectorPackage
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Dev/xilinx acq (#901)

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* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx
This commit is contained in:
maliakal_d
2024-02-07 13:23:08 +01:00
committed by GitHub
parent f6b0ba9703
commit 3d21bb64c4
67 changed files with 3927 additions and 2055 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
slsReceiverSoftware/src/MasterAttributes.cpp
View File

@@ -31,6 +31,9 @@ void MasterAttributes::GetBinaryAttributes(
case slsDetectorDefs::CHIPTESTBOARD:
GetCtbBinaryAttributes(w);
break;
case slsDetectorDefs::XILINX_CHIPTESTBOARD:
GetXilinxCtbBinaryAttributes(w);
break;
default:
throw RuntimeError("Unknown Detector type to get master attributes");
}
@@ -63,6 +66,9 @@ void MasterAttributes::WriteHDF5Attributes(H5::H5File *fd, H5::Group *group) {
case slsDetectorDefs::CHIPTESTBOARD:
WriteCtbHDF5Attributes(fd, group);
break;
case slsDetectorDefs::XILINX_CHIPTESTBOARD:
WriteXilinxCtbHDF5Attributes(fd, group);
break;
default:
throw RuntimeError("Unknown Detector type to get master attributes");
}
@@ -814,4 +820,49 @@ void MasterAttributes::WriteCtbHDF5Attributes(H5::H5File *fd,
}
#endif
void MasterAttributes::GetXilinxCtbBinaryAttributes(
rapidjson::PrettyWriter<rapidjson::StringBuffer> *w) {
w->Key("Exptime");
w->String(ToString(exptime).c_str());
w->Key("Period");
w->String(ToString(period).c_str());
w->Key("ADC Mask");
w->String(ToStringHex(adcmask).c_str());
w->Key("Analog Flag");
w->Uint(analog);
w->Key("Analog Samples");
w->Uint(analogSamples);
w->Key("Digital Flag");
w->Uint(digital);
w->Key("Digital Samples");
w->Uint(digitalSamples);
w->Key("Dbit Offset");
w->Uint(dbitoffset);
w->Key("Dbit Bitset");
w->Uint64(dbitlist);
w->Key("Transceiver Mask");
w->String(ToStringHex(transceiverMask).c_str());
w->Key("Transceiver Flag");
w->Uint(transceiver);
w->Key("Transceiver Samples");
w->Uint(transceiverSamples);
}
#ifdef HDF5C
void MasterAttributes::WriteXilinxCtbHDF5Attributes(H5::H5File *fd,
H5::Group *group) {
MasterAttributes::WriteHDF5Exptime(fd, group);
MasterAttributes::WriteHDF5Period(fd, group);
MasterAttributes::WriteHDF5AdcMask(fd, group);
MasterAttributes::WriteHDF5AnalogFlag(fd, group);
MasterAttributes::WriteHDF5AnalogSamples(fd, group);
MasterAttributes::WriteHDF5DigitalFlag(fd, group);
MasterAttributes::WriteHDF5DigitalSamples(fd, group);
MasterAttributes::WriteHDF5DbitOffset(fd, group);
MasterAttributes::WriteHDF5DbitList(fd, group);
MasterAttributes::WriteHDF5TransceiverMask(fd, group);
MasterAttributes::WriteHDF5TransceiverFlag(fd, group);
MasterAttributes::WriteHDF5TransceiverSamples(fd, group);
}
#endif
} // namespace sls