Dev/xilinx acq (#901)

* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx
This commit is contained in:
2024-02-07 13:23:08 +01:00
committed by GitHub
parent f6b0ba9703
commit 3d21bb64c4
67 changed files with 3927 additions and 2055 deletions

View File

@ -116,6 +116,7 @@ void Implementation::setDetectorType(const detectorType d) {
case JUNGFRAU:
case MOENCH:
case CHIPTESTBOARD:
case XILINX_CHIPTESTBOARD:
case MYTHEN3:
case GOTTHARD2:
LOG(logINFO) << " ***** " << ToString(d) << " Receiver *****";
@ -145,6 +146,9 @@ void Implementation::setDetectorType(const detectorType d) {
case CHIPTESTBOARD:
generalData = new ChipTestBoardData();
break;
case XILINX_CHIPTESTBOARD:
generalData = new XilinxChipTestBoardData();
break;
case MYTHEN3:
generalData = new Mythen3Data();
break;