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Dev/xilinx acq (#901)

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* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx
This commit is contained in:
maliakal_d
2024-02-07 13:23:08 +01:00
committed by GitHub
parent f6b0ba9703
commit 3d21bb64c4
67 changed files with 3927 additions and 2055 deletions
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5
slsDetectorSoftware/tests/Caller/test-Caller-pattern.cpp
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@ -81,9 +81,10 @@ TEST_CASE("Caller::patioctrl", "[.cmdcall]") {
Caller caller(&det);
auto det_type = det.getDetectorType().squash();
if (det_type == defs::CHIPTESTBOARD) {
if (det_type == defs::CHIPTESTBOARD ||
det_type == defs::XILINX_CHIPTESTBOARD) {
auto prev_val = det.getPatternIOControl();
{
if (det_type == defs::CHIPTESTBOARD) {
std::ostringstream oss;
caller.call("patioctrl", {"0xc15004808d0a21a4"}, -1, PUT, oss);
REQUIRE(oss.str() == "patioctrl 0xc15004808d0a21a4\n");