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Dev/xilinx acq (#901)

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* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx
This commit is contained in:
maliakal_d
2024-02-07 13:23:08 +01:00
committed by GitHub
parent f6b0ba9703
commit 3d21bb64c4
67 changed files with 3927 additions and 2055 deletions
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228
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
View File

@ -2,28 +2,48 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
#define CTRLREG1 (0x0)
#define CTRL_REG (0x0)
#define CTRLREG2 (0x4)
#define POWER_VIO_OFST (0)
#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
#define POWER_VCC_A_OFST (1)
#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
#define POWER_VCC_B_OFST (2)
#define POWER_VCC_B_MSK (0x00000001 << POWER_VCC_B_OFST)
#define POWER_VCC_C_OFST (3)
#define POWER_VCC_C_MSK (0x00000001 << POWER_VCC_C_OFST)
#define POWER_VCC_D_OFST (4)
#define POWER_VCC_D_MSK (0x00000001 << POWER_VCC_D_OFST)
#define EMPTY4REG (0x4)
#define STATUSREG1 (0x8)
#define TRANSMISSIONBUSY_OFST (0)
#define TRANSMISSIONBUSY_MSK (0x00000001 << TRANSMISSIONBUSY_OFST)
#define STATUSREG2 (0xC)
#define FPGAVERSIONREG (0x10)
#define COMPDATE_OFST (0)
#define COMPDATE_MSK (0x00ffffff << COMPDATE_OFST)
#define DETTYPE_OFST (24)
#define DETTYPE_MSK (0x000000ff << DETTYPE_OFST)
#define FPGACOMPDATE_OFST (0)
#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define EMPTY14REG (0x14)
#define EMPTY18REG (0x18)
#define FIXEDPATTERNREG (0x18)
#define FIXEDPATTERNVAL (0xACDC2016)
#define EMPTY1CREG (0x1C)
#define EMPTY20REG (0x20)
#define APIVERSIONREG (0x20)
#define APICOMPDATE_OFST (0)
#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
#define APIDETTYPE_OFST (24)
#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
#define EMPTY24REG (0x24)
@ -112,75 +132,75 @@
#define EMPTY9CREG (0x9C)
#define FLOWSTATUSREG (0x100)
#define FLOW_STATUS_REG (0x100)
#define RSMBUSY_OFST (0)
#define RSMBUSY_MSK (0x00000001 << RSMBUSY_OFST)
#define RSMTRGWAIT_OFST (3)
#define RSMTRGWAIT_MSK (0x00000001 << RSMTRGWAIT_OFST)
#define CSMBUSY_OFST (17)
#define CSMBUSY_MSK (0x00000001 << CSMBUSY_OFST)
#define RSM_BUSY_OFST (0)
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
#define RSM_TRG_WAIT_OFST (3)
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
#define CSM_BUSY_OFST (17)
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
#define EMPTY104REG (0x104)
#define FLOWCONTROLREG (0x108)
#define FLOW_CONTROL_REG (0x108)
#define STARTF_OFST (0)
#define STARTF_MSK (0x00000001 << STARTF_OFST)
#define STOPF_OFST (1)
#define STOPF_MSK (0x00000001 << STOPF_OFST)
#define RSTF_OFST (2)
#define RSTF_MSK (0x00000001 << RSTF_OFST)
#define SWTRIGGERF_OFST (3)
#define SWTRIGGERF_MSK (0x00000001 << SWTRIGGERF_OFST)
#define TRIGGERENABLE_OFST (4)
#define TRIGGERENABLE_MSK (0x00000001 << TRIGGERENABLE_OFST)
#define START_F_OFST (0)
#define START_F_MSK (0x00000001 << START_F_OFST)
#define STOP_F_OFST (1)
#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
#define RST_F_OFST (2)
#define RST_F_MSK (0x00000001 << RST_F_OFST)
#define SW_TRIGGER_F_OFST (3)
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
#define TRIGGER_ENABLE_OFST (4)
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
#define EMPTY10CREG (0x10C)
#define TIMEFROMSTARTOUTREG1 (0x110)
#define TIME_FROM_START_OUT_REG_1 (0x110)
#define TIMEFROMSTARTOUTREG2 (0x114)
#define TIME_FROM_START_OUT_REG_2 (0x114)
#define FRAMESFROMSTARTOUTREG1 (0x118)
#define FRAMES_FROM_START_OUT_REG_1 (0x118)
#define FRAMESFROMSTARTOUTREG2 (0x11C)
#define FRAMES_FROM_START_OUT_REG_2 (0x11C)
#define FRAMETIMEOUTREG1 (0x120)
#define FRAME_TIME_OUT_REG_1 (0x120)
#define FRAMETIMEOUTREG2 (0x124)
#define FRAME_TIME_OUT_REG_2 (0x124)
#define DELAYOUTREG1 (0x128)
#define DELAY_OUT_REG_1 (0x128)
#define DELAYOUTREG2 (0x12C)
#define DELAY_OUT_REG_2 (0x12C)
#define CYCLESOUTREG1 (0x130)
#define CYCLES_OUT_REG_1 (0x130)
#define CYCLESOUTREG2 (0x134)
#define CYCLES_OUT_REG_2 (0x134)
#define FRAMESOUTREG1 (0x138)
#define FRAMES_OUT_REG_1 (0x138)
#define FRAMESOUTREG2 (0x13C)
#define FRAMES_OUT_REG_2 (0x13C)
#define PERIODOUTREG1 (0x140)
#define PERIOD_OUT_REG_1 (0x140)
#define PERIODOUTREG2 (0x144)
#define PERIOD_OUT_REG_2 (0x144)
#define DELAYINREG1 (0x148)
#define DELAY_IN_REG_1 (0x148)
#define DELAYINREG2 (0x14C)
#define DELAY_IN_REG_2 (0x14C)
#define CYCLESINREG1 (0x150)
#define CYCLES_IN_REG_1 (0x150)
#define CYCLESINREG2 (0x154)
#define CYCLES_IN_REG_2 (0x154)
#define FRAMESINREG1 (0x158)
#define FRAMES_IN_REG_1 (0x158)
#define FRAMESINREG2 (0x15C)
#define FRAMES_IN_REG_2 (0x15C)
#define PERIODINREG1 (0x160)
#define PERIOD_IN_REG_1 (0x160)
#define PERIODINREG2 (0x164)
#define PERIOD_IN_REG_2 (0x164)
#define EMPTY168REG (0x168)
@ -484,18 +504,15 @@
#define EMPTY3FCREG (0x3FC)
#define EXPCTRLREG (0x400)
#define STARTP_OFST (0)
#define STARTP_MSK (0x00000001 << STARTP_OFST)
#define EMPTY400REG (0x400)
#define EMPTY404REG (0x404)
#define EXPFRAMESREG (0x408)
#define EMPTY408REG (0x408)
#define EMPTY40CREG (0x40C)
#define EXPTIMEREG (0x410)
#define EMPTY410REG (0x410)
#define EMPTY414REG (0x414)
@ -615,47 +632,56 @@
#define EMPTY4FCREG (0x4FC)
#define FIFOTOGBCONTROLREG (0x500)
#define FIFO_TO_GB_CONTROL_REG (0x500)
#define ENABLEDCHANNELS_OFST (0)
#define ENABLEDCHANNELS_MSK (0x00001fff << ENABLEDCHANNELS_OFST)
#define ROMODE_OFST (13)
#define ROMODE_MSK (0x00000007 << ROMODE_OFST)
#define COUNTFRAMESFROMUPDATE_OFST (16)
#define COUNTFRAMESFROMUPDATE_MSK (0x00000001 << COUNTFRAMESFROMUPDATE_OFST)
#define STARTSTREAMING_P_OFST (17)
#define STARTSTREAMING_P_MSK (0x00000001 << STARTSTREAMING_P_OFST)
#define ENABLED_CHANNELS_ADC_OFST (0)
#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
#define ENABLED_CHANNELS_D_OFST (8)
#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
#define ENABLED_CHANNELS_X_OFST (9)
#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
#define RO_MODE_ADC_OFST (13)
#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
#define RO_MODE_D_OFST (14)
#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
#define RO_MODE_X_OFST (15)
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
#define COUNT_FRAMES_FROM_UPDATE_MSK \
(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
#define START_STREAMING_P_OFST (17)
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
#define EMPTY504REG (0x504)
#define NOSAMPLESDREG (0x508)
#define NO_SAMPLES_D_REG (0x508)
#define NOSAMPLESD_OFST (0)
#define NOSAMPLESD_MSK (0x00003fff << NOSAMPLESD_OFST)
#define NO_SAMPLES_D_OFST (0)
#define NO_SAMPLES_D_MSK (0x00003fff << NO_SAMPLES_D_OFST)
#define EMPTY50CREG (0x50C)
#define NOSAMPLESAREG (0x510)
#define NO_SAMPLES_A_REG (0x510)
#define NOSAMPLESA_OFST (0)
#define NOSAMPLESA_MSK (0x00003fff << NOSAMPLESA_OFST)
#define NO_SAMPLES_A_OFST (0)
#define NO_SAMPLES_A_MSK (0x00003fff << NO_SAMPLES_A_OFST)
#define EMPTY514REG (0x514)
#define NOSAMPLESXREG (0x518)
#define NO_SAMPLES_X_REG (0x518)
#define NOSAMPLESX_OFST (0)
#define NOSAMPLESX_MSK (0x00001fff << NOSAMPLESX_OFST)
#define NO_SAMPLES_X_OFST (0)
#define NO_SAMPLES_X_MSK (0x00001fff << NO_SAMPLES_X_OFST)
#define EMPTY51CREG (0x51C)
#define COUNTFRAMESFROMREG1 (0x520)
#define COUNT_FRAMES_FROM_REG_1 (0x520)
#define COUNTFRAMESFROMREG2 (0x524)
#define COUNT_FRAMES_FROM_REG_2 (0x524)
#define LOCALFRAMENUMBERREG1 (0x528)
#define LOCAL_FRAME_NUMBER_REG_1 (0x528)
#define LOCALFRAMENUMBERREG2 (0x52C)
#define LOCAL_FRAME_NUMBER_REG_2 (0x52C)
#define EMPTY530REG (0x530)
@ -697,51 +723,75 @@
#define EMPTY57CREG (0x57C)
#define EMPTY580REG (0x580)
#define A_FIFO_OVERFLOW_STATUS_REG (0x580)
#define EMPTY584REG (0x584)
#define EMPTY588REG (0x588)
#define A_FIFO_EMPTY_STATUS_REG (0x588)
#define EMPTY58CREG (0x58C)
#define EMPTY590REG (0x590)
#define A_FIFO_FULL_STATUS_REG (0x590)
#define EMPTY594REG (0x594)
#define EMPTY598REG (0x598)
#define D_FIFO_OVERFLOW_STATUS_REG (0x598)
#define D_FIFO_OVERFLOW_STATUS_OFST (0)
#define D_FIFO_OVERFLOW_STATUS_MSK (0x00000001 << D_FIFO_OVERFLOW_STATUS_OFST)
#define EMPTY59CREG (0x59C)
#define EMPTY5A0REG (0x5A0)
#define D_FIFO_EMPTY_STATUS_REG (0x5A0)
#define D_FIFO_EMPTY_STATUS_OFST (0)
#define D_FIFO_EMPTY_STATUS_MSK (0x00000001 << D_FIFO_EMPTY_STATUS_OFST)
#define EMPTY5A4REG (0x5A4)
#define EMPTY5A8REG (0x5A8)
#define D_FIFO_FULL_STATUS_REG (0x5A8)
#define D_FIFO_FULL_STATUS_OFST (0)
#define D_FIFO_FULL_STATUS_MSK (0x00000001 << D_FIFO_FULL_STATUS_OFST)
#define EMPTY5ACREG (0x5AC)
#define EMPTY5B0REG (0x5B0)
#define X_FIFO_OVERFLOW_STATUS_REG (0x5B0)
#define X_FIFO_OVERFLOW_STATUS_OFST (0)
#define X_FIFO_OVERFLOW_STATUS_MSK (0x0000000f << X_FIFO_OVERFLOW_STATUS_OFST)
#define EMPTY5B4REG (0x5B4)
#define EMPTY5B8REG (0x5B8)
#define X_FIFO_EMPTY_STATUS_REG (0x5B8)
#define X_FIFO_EMPTY_STATUS_OFST (0)
#define X_FIFO_EMPTY_STATUS_MSK (0x0000000f << X_FIFO_EMPTY_STATUS_OFST)
#define EMPTY5BCREG (0x5BC)
#define EMPTY5C0REG (0x5C0)
#define X_FIFO_FULL_STATUS_REG (0x5C0)
#define X_FIFO_FULL_STATUS_OFST (0)
#define X_FIFO_FULL_STATUS_MSK (0x0000000f << X_FIFO_FULL_STATUS_OFST)
#define EMPTY5C4REG (0x5C4)
#define EMPTY5C8REG (0x5C8)
#define A_FIFO_CLEAN_REG (0x5C8)
#define EMPTY5CCREG (0x5CC)
#define EMPTY5D0REG (0x5D0)
#define D_FIFO_CLEAN_REG (0x5D0)
#define D_FIFO_CLEAN_OFST (0)
#define D_FIFO_CLEAN_MSK (0x00000001 << D_FIFO_CLEAN_OFST)
#define EMPTY5D4REG (0x5D4)
#define EMPTY5D8REG (0x5D8)
#define X_FIFO_CLEAN_REG (0x5D8)
#define X_FIFO_CLEAN_OFST (0)
#define X_FIFO_CLEAN_MSK (0x0000000f << X_FIFO_CLEAN_OFST)
#define EMPTY5DCREG (0x5DC)
@ -777,6 +827,8 @@
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
#define BUSY_OFST (4)
#define BUSY_MSK (0x00000001 << BUSY_OFST)
#define READOUTFROMASIC_OFST (5)
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
#define EMPTY60CREG (0x60C)