mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-16 03:20:14 +01:00
Dev/xilinx acq (#901)
* period and exptime(patternwaittime level 0) * added new regsieterdefs and updated api version and fixedpattern reg * autogenerate commands * formatting * minor * wip resetflow, readout mode, transceiver mask, transceiver enable * acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw * programming fpga and device tree done * most configuration done, need to connect configuretransceiver to client * stuck at resetting transciever timed out * minor * fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber * configuretransceiver from client, added help in client * make formatt and command generation * tests for xilinx ctb works * command generation * dacs added and tested, power not done * power added * added temp_fpga * binaries in * ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed * start works * virtual server sends * receiver works * tests * python function and enum generation, commands generatorn and autocomplete, formatting, tests * tests fail at start(transceiver not aligned) * tests passed * all binaries compiled * eiger binary in * added --nomodule cehck for xilinx
This commit is contained in:
GitHub
@@ -9,7 +9,10 @@ add_executable(xilinx_ctbDetectorServer_virtual
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../slsDetectorServer/src/common.c
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../slsDetectorServer/src/sharedMemory.c
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../slsDetectorServer/src/loadPattern.c
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../slsDetectorServer/src/programViaArm.c
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../slsDetectorServer/src/communication_funcs_UDP.c
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../../slsSupportLib/src/md5.c
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../slsDetectorServer/src/LTC2620_Driver.c
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)
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include_directories(
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@@ -23,11 +26,11 @@ target_include_directories(xilinx_ctbDetectorServer_virtual
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)
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target_compile_definitions(xilinx_ctbDetectorServer_virtual
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PUBLIC XILINX_CHIPTESTBOARDD ARMPROCESSOR VIRTUAL STOP_SERVER
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PUBLIC XILINX_CHIPTESTBOARDD ARMPROCESSOR VIRTUAL STOP_SERVER
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)
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target_link_libraries(xilinx_ctbDetectorServer_virtual
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PUBLIC pthread rt slsProjectCSettings
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PUBLIC pthread rt m slsProjectCSettings
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)
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set_target_properties(xilinx_ctbDetectorServer_virtual PROPERTIES
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@@ -18,7 +18,7 @@ DESTDIR ?= bin
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INSTMODE = 0777
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SRCS = slsDetectorFunctionList.c
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SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c
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SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
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OBJS = $(SRCS:.c=.o)
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@@ -2,28 +2,48 @@
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#define CTRLREG1 (0x0)
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#define CTRL_REG (0x0)
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#define CTRLREG2 (0x4)
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#define POWER_VIO_OFST (0)
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#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
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#define POWER_VCC_A_OFST (1)
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#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
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#define POWER_VCC_B_OFST (2)
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#define POWER_VCC_B_MSK (0x00000001 << POWER_VCC_B_OFST)
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#define POWER_VCC_C_OFST (3)
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#define POWER_VCC_C_MSK (0x00000001 << POWER_VCC_C_OFST)
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#define POWER_VCC_D_OFST (4)
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#define POWER_VCC_D_MSK (0x00000001 << POWER_VCC_D_OFST)
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#define EMPTY4REG (0x4)
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#define STATUSREG1 (0x8)
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#define TRANSMISSIONBUSY_OFST (0)
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#define TRANSMISSIONBUSY_MSK (0x00000001 << TRANSMISSIONBUSY_OFST)
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#define STATUSREG2 (0xC)
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#define FPGAVERSIONREG (0x10)
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#define COMPDATE_OFST (0)
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#define COMPDATE_MSK (0x00ffffff << COMPDATE_OFST)
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#define DETTYPE_OFST (24)
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#define DETTYPE_MSK (0x000000ff << DETTYPE_OFST)
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#define FPGACOMPDATE_OFST (0)
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#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define EMPTY14REG (0x14)
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#define EMPTY18REG (0x18)
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#define FIXEDPATTERNREG (0x18)
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#define FIXEDPATTERNVAL (0xACDC2016)
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#define EMPTY1CREG (0x1C)
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#define EMPTY20REG (0x20)
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#define APIVERSIONREG (0x20)
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#define APICOMPDATE_OFST (0)
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#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
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#define APIDETTYPE_OFST (24)
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#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
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#define EMPTY24REG (0x24)
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@@ -112,75 +132,75 @@
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#define EMPTY9CREG (0x9C)
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#define FLOWSTATUSREG (0x100)
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#define FLOW_STATUS_REG (0x100)
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#define RSMBUSY_OFST (0)
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#define RSMBUSY_MSK (0x00000001 << RSMBUSY_OFST)
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#define RSMTRGWAIT_OFST (3)
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#define RSMTRGWAIT_MSK (0x00000001 << RSMTRGWAIT_OFST)
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#define CSMBUSY_OFST (17)
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#define CSMBUSY_MSK (0x00000001 << CSMBUSY_OFST)
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#define RSM_BUSY_OFST (0)
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#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
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#define RSM_TRG_WAIT_OFST (3)
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#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
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#define CSM_BUSY_OFST (17)
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#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
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#define EMPTY104REG (0x104)
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#define FLOWCONTROLREG (0x108)
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#define FLOW_CONTROL_REG (0x108)
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#define STARTF_OFST (0)
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#define STARTF_MSK (0x00000001 << STARTF_OFST)
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#define STOPF_OFST (1)
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#define STOPF_MSK (0x00000001 << STOPF_OFST)
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#define RSTF_OFST (2)
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#define RSTF_MSK (0x00000001 << RSTF_OFST)
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#define SWTRIGGERF_OFST (3)
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#define SWTRIGGERF_MSK (0x00000001 << SWTRIGGERF_OFST)
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#define TRIGGERENABLE_OFST (4)
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#define TRIGGERENABLE_MSK (0x00000001 << TRIGGERENABLE_OFST)
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#define START_F_OFST (0)
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#define START_F_MSK (0x00000001 << START_F_OFST)
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#define STOP_F_OFST (1)
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#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
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#define RST_F_OFST (2)
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#define RST_F_MSK (0x00000001 << RST_F_OFST)
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#define SW_TRIGGER_F_OFST (3)
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#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
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#define TRIGGER_ENABLE_OFST (4)
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#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
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#define EMPTY10CREG (0x10C)
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#define TIMEFROMSTARTOUTREG1 (0x110)
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#define TIME_FROM_START_OUT_REG_1 (0x110)
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#define TIMEFROMSTARTOUTREG2 (0x114)
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#define TIME_FROM_START_OUT_REG_2 (0x114)
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#define FRAMESFROMSTARTOUTREG1 (0x118)
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#define FRAMES_FROM_START_OUT_REG_1 (0x118)
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#define FRAMESFROMSTARTOUTREG2 (0x11C)
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#define FRAMES_FROM_START_OUT_REG_2 (0x11C)
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#define FRAMETIMEOUTREG1 (0x120)
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#define FRAME_TIME_OUT_REG_1 (0x120)
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#define FRAMETIMEOUTREG2 (0x124)
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#define FRAME_TIME_OUT_REG_2 (0x124)
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#define DELAYOUTREG1 (0x128)
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#define DELAY_OUT_REG_1 (0x128)
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#define DELAYOUTREG2 (0x12C)
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#define DELAY_OUT_REG_2 (0x12C)
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#define CYCLESOUTREG1 (0x130)
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#define CYCLES_OUT_REG_1 (0x130)
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#define CYCLESOUTREG2 (0x134)
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#define CYCLES_OUT_REG_2 (0x134)
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#define FRAMESOUTREG1 (0x138)
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#define FRAMES_OUT_REG_1 (0x138)
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#define FRAMESOUTREG2 (0x13C)
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#define FRAMES_OUT_REG_2 (0x13C)
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#define PERIODOUTREG1 (0x140)
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#define PERIOD_OUT_REG_1 (0x140)
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#define PERIODOUTREG2 (0x144)
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#define PERIOD_OUT_REG_2 (0x144)
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#define DELAYINREG1 (0x148)
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#define DELAY_IN_REG_1 (0x148)
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#define DELAYINREG2 (0x14C)
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#define DELAY_IN_REG_2 (0x14C)
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#define CYCLESINREG1 (0x150)
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#define CYCLES_IN_REG_1 (0x150)
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#define CYCLESINREG2 (0x154)
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#define CYCLES_IN_REG_2 (0x154)
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#define FRAMESINREG1 (0x158)
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#define FRAMES_IN_REG_1 (0x158)
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#define FRAMESINREG2 (0x15C)
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#define FRAMES_IN_REG_2 (0x15C)
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#define PERIODINREG1 (0x160)
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#define PERIOD_IN_REG_1 (0x160)
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#define PERIODINREG2 (0x164)
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#define PERIOD_IN_REG_2 (0x164)
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#define EMPTY168REG (0x168)
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@@ -484,18 +504,15 @@
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#define EMPTY3FCREG (0x3FC)
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#define EXPCTRLREG (0x400)
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#define STARTP_OFST (0)
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#define STARTP_MSK (0x00000001 << STARTP_OFST)
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#define EMPTY400REG (0x400)
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#define EMPTY404REG (0x404)
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#define EXPFRAMESREG (0x408)
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#define EMPTY408REG (0x408)
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#define EMPTY40CREG (0x40C)
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#define EXPTIMEREG (0x410)
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#define EMPTY410REG (0x410)
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#define EMPTY414REG (0x414)
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@@ -615,47 +632,56 @@
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#define EMPTY4FCREG (0x4FC)
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#define FIFOTOGBCONTROLREG (0x500)
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#define FIFO_TO_GB_CONTROL_REG (0x500)
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#define ENABLEDCHANNELS_OFST (0)
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#define ENABLEDCHANNELS_MSK (0x00001fff << ENABLEDCHANNELS_OFST)
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#define ROMODE_OFST (13)
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#define ROMODE_MSK (0x00000007 << ROMODE_OFST)
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#define COUNTFRAMESFROMUPDATE_OFST (16)
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#define COUNTFRAMESFROMUPDATE_MSK (0x00000001 << COUNTFRAMESFROMUPDATE_OFST)
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#define STARTSTREAMING_P_OFST (17)
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#define STARTSTREAMING_P_MSK (0x00000001 << STARTSTREAMING_P_OFST)
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#define ENABLED_CHANNELS_ADC_OFST (0)
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#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
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#define ENABLED_CHANNELS_D_OFST (8)
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#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
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#define ENABLED_CHANNELS_X_OFST (9)
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#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
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#define RO_MODE_ADC_OFST (13)
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#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
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#define RO_MODE_D_OFST (14)
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#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
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#define RO_MODE_X_OFST (15)
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#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
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#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
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#define COUNT_FRAMES_FROM_UPDATE_MSK \
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(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
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#define START_STREAMING_P_OFST (17)
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#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
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#define EMPTY504REG (0x504)
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#define NOSAMPLESDREG (0x508)
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#define NO_SAMPLES_D_REG (0x508)
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#define NOSAMPLESD_OFST (0)
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#define NOSAMPLESD_MSK (0x00003fff << NOSAMPLESD_OFST)
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#define NO_SAMPLES_D_OFST (0)
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#define NO_SAMPLES_D_MSK (0x00003fff << NO_SAMPLES_D_OFST)
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#define EMPTY50CREG (0x50C)
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#define NOSAMPLESAREG (0x510)
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#define NO_SAMPLES_A_REG (0x510)
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#define NOSAMPLESA_OFST (0)
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#define NOSAMPLESA_MSK (0x00003fff << NOSAMPLESA_OFST)
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#define NO_SAMPLES_A_OFST (0)
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#define NO_SAMPLES_A_MSK (0x00003fff << NO_SAMPLES_A_OFST)
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#define EMPTY514REG (0x514)
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#define NOSAMPLESXREG (0x518)
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#define NO_SAMPLES_X_REG (0x518)
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#define NOSAMPLESX_OFST (0)
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#define NOSAMPLESX_MSK (0x00001fff << NOSAMPLESX_OFST)
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#define NO_SAMPLES_X_OFST (0)
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#define NO_SAMPLES_X_MSK (0x00001fff << NO_SAMPLES_X_OFST)
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#define EMPTY51CREG (0x51C)
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#define COUNTFRAMESFROMREG1 (0x520)
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#define COUNT_FRAMES_FROM_REG_1 (0x520)
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#define COUNTFRAMESFROMREG2 (0x524)
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#define COUNT_FRAMES_FROM_REG_2 (0x524)
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#define LOCALFRAMENUMBERREG1 (0x528)
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#define LOCAL_FRAME_NUMBER_REG_1 (0x528)
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#define LOCALFRAMENUMBERREG2 (0x52C)
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#define LOCAL_FRAME_NUMBER_REG_2 (0x52C)
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#define EMPTY530REG (0x530)
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@@ -697,51 +723,75 @@
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#define EMPTY57CREG (0x57C)
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#define EMPTY580REG (0x580)
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#define A_FIFO_OVERFLOW_STATUS_REG (0x580)
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#define EMPTY584REG (0x584)
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#define EMPTY588REG (0x588)
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#define A_FIFO_EMPTY_STATUS_REG (0x588)
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#define EMPTY58CREG (0x58C)
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#define EMPTY590REG (0x590)
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#define A_FIFO_FULL_STATUS_REG (0x590)
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#define EMPTY594REG (0x594)
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#define EMPTY598REG (0x598)
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#define D_FIFO_OVERFLOW_STATUS_REG (0x598)
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#define D_FIFO_OVERFLOW_STATUS_OFST (0)
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#define D_FIFO_OVERFLOW_STATUS_MSK (0x00000001 << D_FIFO_OVERFLOW_STATUS_OFST)
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#define EMPTY59CREG (0x59C)
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#define EMPTY5A0REG (0x5A0)
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#define D_FIFO_EMPTY_STATUS_REG (0x5A0)
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#define D_FIFO_EMPTY_STATUS_OFST (0)
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#define D_FIFO_EMPTY_STATUS_MSK (0x00000001 << D_FIFO_EMPTY_STATUS_OFST)
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#define EMPTY5A4REG (0x5A4)
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#define EMPTY5A8REG (0x5A8)
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#define D_FIFO_FULL_STATUS_REG (0x5A8)
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||||
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#define D_FIFO_FULL_STATUS_OFST (0)
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#define D_FIFO_FULL_STATUS_MSK (0x00000001 << D_FIFO_FULL_STATUS_OFST)
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#define EMPTY5ACREG (0x5AC)
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#define EMPTY5B0REG (0x5B0)
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#define X_FIFO_OVERFLOW_STATUS_REG (0x5B0)
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#define X_FIFO_OVERFLOW_STATUS_OFST (0)
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#define X_FIFO_OVERFLOW_STATUS_MSK (0x0000000f << X_FIFO_OVERFLOW_STATUS_OFST)
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||||
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#define EMPTY5B4REG (0x5B4)
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#define EMPTY5B8REG (0x5B8)
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#define X_FIFO_EMPTY_STATUS_REG (0x5B8)
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#define X_FIFO_EMPTY_STATUS_OFST (0)
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#define X_FIFO_EMPTY_STATUS_MSK (0x0000000f << X_FIFO_EMPTY_STATUS_OFST)
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||||
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#define EMPTY5BCREG (0x5BC)
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||||
|
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#define EMPTY5C0REG (0x5C0)
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#define X_FIFO_FULL_STATUS_REG (0x5C0)
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||||
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#define X_FIFO_FULL_STATUS_OFST (0)
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||||
#define X_FIFO_FULL_STATUS_MSK (0x0000000f << X_FIFO_FULL_STATUS_OFST)
|
||||
|
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#define EMPTY5C4REG (0x5C4)
|
||||
|
||||
#define EMPTY5C8REG (0x5C8)
|
||||
#define A_FIFO_CLEAN_REG (0x5C8)
|
||||
|
||||
#define EMPTY5CCREG (0x5CC)
|
||||
|
||||
#define EMPTY5D0REG (0x5D0)
|
||||
#define D_FIFO_CLEAN_REG (0x5D0)
|
||||
|
||||
#define D_FIFO_CLEAN_OFST (0)
|
||||
#define D_FIFO_CLEAN_MSK (0x00000001 << D_FIFO_CLEAN_OFST)
|
||||
|
||||
#define EMPTY5D4REG (0x5D4)
|
||||
|
||||
#define EMPTY5D8REG (0x5D8)
|
||||
#define X_FIFO_CLEAN_REG (0x5D8)
|
||||
|
||||
#define X_FIFO_CLEAN_OFST (0)
|
||||
#define X_FIFO_CLEAN_MSK (0x0000000f << X_FIFO_CLEAN_OFST)
|
||||
|
||||
#define EMPTY5DCREG (0x5DC)
|
||||
|
||||
@@ -777,6 +827,8 @@
|
||||
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
|
||||
#define BUSY_OFST (4)
|
||||
#define BUSY_MSK (0x00000001 << BUSY_OFST)
|
||||
#define READOUTFROMASIC_OFST (5)
|
||||
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
|
||||
|
||||
#define EMPTY60CREG (0x60C)
|
||||
|
||||
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -4,7 +4,7 @@
|
||||
#include "RegisterDefs.h"
|
||||
#include "sls/sls_detector_defs.h"
|
||||
|
||||
#define REQRD_FRMWRE_VRSN (0x230000)
|
||||
#define REQRD_FRMWRE_VRSN (0x230710)
|
||||
#define KERNEL_DATE_VRSN "Wed Nov 29 17:32:14 CET 2023"
|
||||
|
||||
#define LINKED_SERVER_NAME "xilinx_ctbDetectorServer"
|
||||
@@ -12,16 +12,134 @@
|
||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NCHAN (1)
|
||||
#define NCHAN (40)
|
||||
#define NCHAN_ANALOG (32)
|
||||
#define NCHAN_DIGITAL (64)
|
||||
#define NCHAN_TRANSCEIVER (4)
|
||||
#define NBITS_PER_TRANSCEIVER (64)
|
||||
#define NCHIP (1)
|
||||
#define NDAC (24)
|
||||
#define NPWR (6)
|
||||
#define NDAC_ONLY (NDAC - NPWR)
|
||||
|
||||
enum ADCINDEX { V_PWR_IO };
|
||||
enum DACINDEX { D0 };
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
|
||||
|
||||
#define DAC_DRIVER_NUM_DEVICES (3)
|
||||
#define DAC_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device%d/out_voltage%d_raw")
|
||||
#define DAC_POWERDOWN_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device%d/out_voltage%d_powerdown")
|
||||
|
||||
#define SLOWADC_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device%d/in_voltage%d_raw")
|
||||
//#define SLOWDAC_CONVERTION_FACTOR_TO_UV (62.500953)
|
||||
|
||||
#define TEMP_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device0/in_temp7_input")
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_EXPTIME (0)
|
||||
#define DEFAULT_PERIOD (300 * 1000) // 300us
|
||||
#define DEFAULT_READOUT_MODE (TRANSCEIVER_ONLY)
|
||||
#define DEFAULT_READOUT_MODE_STR "transceiver_only"
|
||||
#define DEFAULT_TRANSCEIVER_MASK (0x3) // TODO: check
|
||||
#define DEFAULT_NUM_ASAMPLES (1)
|
||||
#define DEFAULT_NUM_DSAMPLES (1)
|
||||
#define DEFAULT_NUM_TSAMPLES (200)
|
||||
#define DEFAULT_STARTING_FRAME_NUMBER (1)
|
||||
#define DEFAULT_VLIMIT (-100)
|
||||
#define DEFAULT_DELAY (0)
|
||||
|
||||
#define MAX_TRANSCEIVER_MASK (0xF)
|
||||
#define MAX_TRANSCEIVER_SAMPLES (0x1FFF)
|
||||
|
||||
#define MAX_ANALOG_SAMPLES (0x3FFF)
|
||||
#define MAX_DIGITAL_SAMPLES (0x3FFF)
|
||||
|
||||
#define DAC_MIN_MV (0)
|
||||
#define DAC_MAX_MV (2500)
|
||||
|
||||
#define TICK_CLK (20) // MHz (trig_timeFromStart, frametime, timeFromStart)
|
||||
#define RUN_CLK \
|
||||
(100) // MHz (framesFromStart, c_swTrigger, run, waitForTrigger, starting,
|
||||
// acquiring, waitForPeriod, internalStop, c_framesFromSTart_reset,
|
||||
// s_start, c_stop, triggerEnable, period, frames, cycles, delay)
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_OUT_0US_TIMES (35000) // 2s
|
||||
|
||||
#define BIT32_MSK (0xFFFFFFFF)
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
#define MAX_DATA_SIZE_IN_PACKET (8144)
|
||||
|
||||
/* Enum Definitions */
|
||||
enum ADCINDEX {
|
||||
S_ADC0,
|
||||
S_ADC1,
|
||||
S_ADC2,
|
||||
S_ADC3,
|
||||
S_ADC4,
|
||||
S_ADC5,
|
||||
S_ADC6,
|
||||
S_ADC7,
|
||||
TEMP_FPGA
|
||||
};
|
||||
enum DACINDEX {
|
||||
D0,
|
||||
D1,
|
||||
D2,
|
||||
D3,
|
||||
D4,
|
||||
D5,
|
||||
D6,
|
||||
D7,
|
||||
D8,
|
||||
D9,
|
||||
D10,
|
||||
D11,
|
||||
D12,
|
||||
D13,
|
||||
D14,
|
||||
D15,
|
||||
D16,
|
||||
D17,
|
||||
D_PWR_D,
|
||||
D_PWR_EMPTY,
|
||||
D_PWR_IO,
|
||||
D_PWR_A,
|
||||
D_PWR_B,
|
||||
D_PWR_C
|
||||
};
|
||||
|
||||
/* Struct Definitions */
|
||||
typedef struct udp_header_struct {
|
||||
uint32_t udp_destmac_msb;
|
||||
uint16_t udp_srcmac_msb;
|
||||
uint16_t udp_destmac_lsb;
|
||||
uint32_t udp_srcmac_lsb;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl : 4, ip_ver : 4;
|
||||
uint16_t udp_ethertype;
|
||||
uint16_t ip_identification;
|
||||
uint16_t ip_totallength;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
|
||||
uint16_t ip_srcip_msb;
|
||||
uint16_t ip_checksum;
|
||||
uint16_t ip_destip_msb;
|
||||
uint16_t ip_srcip_lsb;
|
||||
uint16_t udp_srcport;
|
||||
uint16_t ip_destip_lsb;
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
} udp_header;
|
||||
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
|
||||
Reference in New Issue
Block a user