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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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Dev/xilinx acq (#901)
* period and exptime(patternwaittime level 0) * added new regsieterdefs and updated api version and fixedpattern reg * autogenerate commands * formatting * minor * wip resetflow, readout mode, transceiver mask, transceiver enable * acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw * programming fpga and device tree done * most configuration done, need to connect configuretransceiver to client * stuck at resetting transciever timed out * minor * fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber * configuretransceiver from client, added help in client * make formatt and command generation * tests for xilinx ctb works * command generation * dacs added and tested, power not done * power added * added temp_fpga * binaries in * ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed * start works * virtual server sends * receiver works * tests * python function and enum generation, commands generatorn and autocomplete, formatting, tests * tests fail at start(transceiver not aligned) * tests passed * all binaries compiled * eiger binary in * added --nomodule cehck for xilinx
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@ -471,7 +471,8 @@ void setupDetector() {
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// hv
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DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
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// dacs
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LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
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LTC2620_D_SetDefines(DAC_MIN_MV, DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC, 1,
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0, "");
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// on chip dacs
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ASIC_Driver_SetDefines(ONCHIP_DAC_DRIVER_FILE_NAME);
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setTimingSource(DEFAULT_TIMING_SOURCE);
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@ -35,6 +35,7 @@
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#define TEMPERATURE_FILE_NAME ("/sys/class/hwmon/hwmon0/temp1_input")
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#endif
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#define CONFIG_FILE ("config_gotthard2.txt")
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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#define ONCHIP_DAC_MAX_VAL (0x3FF)
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#define ADU_MAX_VAL (0xFFF)
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