Dev/xilinx acq (#901)

* period and exptime(patternwaittime level 0)

* added new regsieterdefs and updated api version and fixedpattern reg

* autogenerate commands

* formatting

* minor

* wip resetflow, readout mode, transceiver mask, transceiver enable

* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw

* programming fpga and device tree done

* most configuration done, need to connect configuretransceiver to client

* stuck at resetting transciever timed out

* minor

* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber

* configuretransceiver from client, added help in client

* make formatt and command generation

* tests for xilinx ctb works

* command generation

* dacs added and tested, power not done

* power added

* added temp_fpga

* binaries in

* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed

* start works

* virtual server sends

* receiver works

* tests

* python function and enum generation, commands generatorn and autocomplete, formatting, tests

* tests fail at start(transceiver not aligned)

* tests passed

* all binaries compiled

* eiger binary in

* added --nomodule cehck for xilinx
This commit is contained in:
2024-02-07 13:23:08 +01:00
committed by GitHub
parent f6b0ba9703
commit 3d21bb64c4
67 changed files with 3927 additions and 2055 deletions

View File

@ -471,7 +471,8 @@ void setupDetector() {
// hv
DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
// dacs
LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
LTC2620_D_SetDefines(DAC_MIN_MV, DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC, 1,
0, "");
// on chip dacs
ASIC_Driver_SetDefines(ONCHIP_DAC_DRIVER_FILE_NAME);
setTimingSource(DEFAULT_TIMING_SOURCE);

View File

@ -35,6 +35,7 @@
#define TEMPERATURE_FILE_NAME ("/sys/class/hwmon/hwmon0/temp1_input")
#endif
#define CONFIG_FILE ("config_gotthard2.txt")
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2048)
#define ONCHIP_DAC_MAX_VAL (0x3FF)
#define ADU_MAX_VAL (0xFFF)