mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-12 04:47:14 +02:00
Dev/xilinx acq (#901)
* period and exptime(patternwaittime level 0) * added new regsieterdefs and updated api version and fixedpattern reg * autogenerate commands * formatting * minor * wip resetflow, readout mode, transceiver mask, transceiver enable * acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw * programming fpga and device tree done * most configuration done, need to connect configuretransceiver to client * stuck at resetting transciever timed out * minor * fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber * configuretransceiver from client, added help in client * make formatt and command generation * tests for xilinx ctb works * command generation * dacs added and tested, power not done * power added * added temp_fpga * binaries in * ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed * start works * virtual server sends * receiver works * tests * python function and enum generation, commands generatorn and autocomplete, formatting, tests * tests fail at start(transceiver not aligned) * tests passed * all binaries compiled * eiger binary in * added --nomodule cehck for xilinx
This commit is contained in:
GitHub
@ -37,8 +37,7 @@ target_compile_definitions(ctbDetectorServer_virtual
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)
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target_link_libraries(ctbDetectorServer_virtual
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PUBLIC pthread rt slsProjectCSettings
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m
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PUBLIC pthread rt m slsProjectCSettings
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)
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set_target_properties(ctbDetectorServer_virtual PROPERTIES
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@ -55,7 +55,9 @@
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#define DEFAULT_SYNC_CLK (40) // 20
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#define DEFAULT_DBIT_CLK (200)
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#define DEFAULT_TRANSCEIVER_MASK (0x3)
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#define MAX_TRANSCEIVER_MASK (0xF)
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#define MAX_TRANSCEIVER_MASK (0xF)
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#define MAX_TRANSCEIVER_SAMPLES (0xFFFF)
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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@ -471,7 +471,8 @@ void setupDetector() {
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// hv
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DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
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// dacs
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LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
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LTC2620_D_SetDefines(DAC_MIN_MV, DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC, 1,
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0, "");
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// on chip dacs
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ASIC_Driver_SetDefines(ONCHIP_DAC_DRIVER_FILE_NAME);
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setTimingSource(DEFAULT_TIMING_SOURCE);
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@ -35,6 +35,7 @@
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#define TEMPERATURE_FILE_NAME ("/sys/class/hwmon/hwmon0/temp1_input")
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#endif
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#define CONFIG_FILE ("config_gotthard2.txt")
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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#define ONCHIP_DAC_MAX_VAL (0x3FF)
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#define ADU_MAX_VAL (0xFFF)
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@ -483,7 +483,8 @@ void setupDetector() {
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// hv
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DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
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// dac
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LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
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LTC2620_D_SetDefines(DAC_MIN_MV, DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC, 1,
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0, "");
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resetCore();
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resetPeripheral();
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@ -34,6 +34,7 @@
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#else
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#define TEMPERATURE_FILE_NAME ("/sys/class/hwmon/hwmon0/temp1_input")
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#endif
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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#define TYPE_MYTHEN3_MODULE_VAL (93)
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#define TYPE_TOLERANCE (5)
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@ -4,18 +4,11 @@
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#include <inttypes.h>
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/**
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* Set Defines
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* @param hardMaxV maximum hardware limit
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* @param driverfname driver file name
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* @param numdacs number of dacs
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*/
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void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs);
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/**
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* Get max number of steps
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*/
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void LTC2620_D_SetDefines(int hardMinV, int hardMaxV, char *driverfname,
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int numdacs, int numdevices, int startingDeviceIndex,
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char *powerdownDriverfname);
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int LTC2620_D_GetMaxNumSteps();
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int LTC2620_D_GetPowerDownValue();
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/**
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* Convert voltage to dac units
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@ -9,4 +9,7 @@ void bus_w(u_int32_t offset, u_int32_t data);
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u_int32_t bus_r(u_int32_t offset);
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uint64_t getU64BitReg(int aLSB, int aMSB);
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void setU64BitReg(uint64_t value, int aLSB, int aMSB);
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u_int32_t readRegister(u_int32_t offset);
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u_int32_t writeRegister(u_int32_t offset, u_int32_t data);
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int mapCSP0(void);
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u_int32_t *Arm_getUDPBaseAddress();
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@ -11,7 +11,7 @@ void initializePatternAddresses();
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void initializePatternWord();
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#endif
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#endif
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#if defined(CHIPTESTBOARDD) // TODO || defined(XILINX_CHIPTESTBOARDD)
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#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
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uint64_t validate_readPatternIOControl();
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int validate_writePatternIOControl(char *message, uint64_t arg);
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void writePatternIOControl(uint64_t word);
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12
slsDetectorServers/slsDetectorServer/include/programViaArm.h
Normal file
12
slsDetectorServers/slsDetectorServer/include/programViaArm.h
Normal file
@ -0,0 +1,12 @@
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// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include <sys/types.h>
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int resetFPGA(char *mess);
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int loadDeviceTree(char *mess, int *adcDeviceIndex, int *dacDeviceIndex);
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int checksBeforeCreatingDeviceTree(char *mess);
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int createDeviceTree(char *mess);
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int verifyDeviceTree(char *mess, int *adcDeviceIndex, int *dacDeviceIndex);
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@ -27,6 +27,7 @@
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#ifdef ARMPROCESSOR
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#include "arm64.h"
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#include "programViaArm.h"
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#endif
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#ifdef MYTHEN3D
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@ -68,8 +69,12 @@ void basictests();
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#if !defined(EIGERD)
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int checkType();
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int testFpga();
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#ifdef XILINX_CHIPTESTBOARDD
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int testFixedFPGAPattern();
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#else
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int testBus();
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#endif
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#endif
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#if defined(GOTTHARDD) || \
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((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
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@ -84,9 +89,7 @@ u_int64_t getFirmwareVersion();
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#ifdef EIGERD
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uint64_t getFrontEndFirmwareVersion(enum fpgaPosition fpgaPosition);
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#endif
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#ifndef XILINX_CHIPTESTBOARDD
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u_int64_t getFirmwareAPIVersion();
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#endif
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void getHardwareVersion(char *version);
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#ifdef EIGERD
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int getHardwareVersionNumber();
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@ -178,6 +181,22 @@ uint32_t readRegister16And32(uint32_t offset);
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#endif
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// firmware functions (resets)
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#if defined(XILINX_CHIPTESTBOARDD)
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void cleanFifos();
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void resetFlow();
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int waitTranseiverReset(char *mess);
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#ifdef VIRTUAL
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void setTransceiverAlignment(int align);
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#endif
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int isTransceiverAligned();
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int waitTransceiverAligned(char *mess);
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int configureTransceiver(char *mess);
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int isChipConfigured();
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int powerChip(int on, char *mess);
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int getPowerChip();
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int configureChip(char *mess);
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void startPeriphery();
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#endif
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#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
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defined(MYTHEN3D) || defined(GOTTHARD2D)
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void cleanFifos();
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@ -217,6 +236,12 @@ uint32_t getTransceiverEnableMask();
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void setADCInvertRegister(uint32_t val);
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uint32_t getADCInvertRegister();
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#endif
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#ifdef XILINX_CHIPTESTBOARDD
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void setADCEnableMask_10G(uint32_t mask);
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uint32_t getADCEnableMask_10G();
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int setTransceiverEnableMask(uint32_t mask);
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uint32_t getTransceiverEnableMask();
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#endif
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#if defined(CHIPTESTBOARDD)
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int setExternalSamplingSource(int val);
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int setExternalSampling(int val);
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@ -232,7 +257,7 @@ int getParallelMode();
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int setOverFlowMode(int mode);
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int getOverFlowMode();
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#endif
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#ifdef CHIPTESTBOARDD
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#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
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int setReadoutMode(enum readoutMode mode);
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int getReadoutMode();
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#endif
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@ -243,7 +268,7 @@ int selectStoragecellStart(int pos);
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int getMaxStoragecellStart();
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#endif
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#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(EIGERD) || \
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defined(CHIPTESTBOARDD)
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defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
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int setNextFrameNumber(uint64_t value);
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int getNextFrameNumber(uint64_t *value);
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#endif
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@ -251,14 +276,12 @@ void setNumFrames(int64_t val);
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int64_t getNumFrames();
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void setNumTriggers(int64_t val);
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int64_t getNumTriggers();
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#ifndef XILINX_CHIPTESTBOARDD
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#ifndef MYTHEN3D
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int setExpTime(int64_t val);
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int64_t getExpTime();
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#endif
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int setPeriod(int64_t val);
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int64_t getPeriod();
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#endif
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#ifdef MYTHEN3D
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void setNumIntGates(int val);
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void setNumGates(int val);
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@ -290,11 +313,9 @@ int getNumAdditionalStorageCells();
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int setStorageCellDelay(int64_t val);
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int64_t getStorageCellDelay();
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#endif
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#if defined(CHIPTESTBOARDD)
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#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
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int setNumAnalogSamples(int val);
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int getNumAnalogSamples();
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#endif
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#ifdef CHIPTESTBOARDD
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int setNumDigitalSamples(int val);
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int getNumDigitalSamples();
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int setNumTransceiverSamples(int val);
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@ -312,10 +333,10 @@ int64_t getNumFramesLeft();
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int64_t getNumTriggersLeft();
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#endif
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#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARDD) || \
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defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
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defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D) || \
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defined(XILINX_CHIPTESTBOARDD)
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int setDelayAfterTrigger(int64_t val);
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int64_t getDelayAfterTrigger();
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int64_t getDelayAfterTriggerLeft();
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int64_t getPeriodLeft();
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#endif
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@ -326,7 +347,7 @@ int64_t getNumBurstsLeft();
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int64_t getExpTimeLeft();
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#endif
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#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
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defined(MYTHEN3D) || defined(GOTTHARD2D)
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defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
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int64_t getFramesFromStart();
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int64_t getActualTime();
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int64_t getMeasurementTime();
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@ -379,15 +400,11 @@ void setDAC(enum DACINDEX ind, int val, int mV, int counterEnableCheck);
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void setGeneralDAC(enum DACINDEX ind, int val, int mV);
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void setVthDac(int index, int enable);
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#else
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#ifndef XILINX_CHIPTESTBOARDD
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void setDAC(enum DACINDEX ind, int val, int mV);
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#endif
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#endif
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#ifndef XILINX_CHIPTESTBOARDD
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int getDAC(enum DACINDEX ind, int mV);
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int getMaxDacSteps();
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#endif
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#if defined(CHIPTESTBOARDD)
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#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
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int dacToVoltage(int dac);
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int checkVLimitCompliant(int mV);
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int checkVLimitDacCompliant(int dac);
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@ -406,20 +423,24 @@ int isPowerValid(enum DACINDEX ind, int val);
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int getPower();
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void setPower(enum DACINDEX ind, int val);
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void powerOff();
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#elif XILINX_CHIPTESTBOARDD
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int getPower();
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void setPower(enum DACINDEX ind, int val);
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#endif
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#if defined(MYTHEN3D) || defined(GOTTHARD2D)
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#if defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
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int getADC(enum ADCINDEX ind, int *value);
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#else
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#ifndef XILINX_CHIPTESTBOARDD
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int getADC(enum ADCINDEX ind);
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#endif
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#endif
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#ifdef CHIPTESTBOARDD
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int getSlowADC(int ichan);
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int getSlowADCTemperature();
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#endif
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#ifndef XILINX_CHIPTESTBOARDD
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#ifdef XILINX_CHIPTESTBOARDD
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int getSlowADC(int ichan, int *retval);
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int getTemperature(int *retval);
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#else
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int setHighVoltage(int val);
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#endif
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@ -491,7 +512,8 @@ void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip,
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uint32_t sourceip, uint16_t sourceport);
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#endif
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#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D) || \
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defined(MYTHEN3D) || defined(CHIPTESTBOARDD)
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defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || \
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defined(XILINX_CHIPTESTBOARDD)
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void calcChecksum(udp_header *udp);
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#endif
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#ifdef GOTTHARDD
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@ -694,30 +716,27 @@ int setTransmissionDelayRight(int value);
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#endif
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// aquisition
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#ifndef XILINX_CHIPTESTBOARDD
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int startStateMachine();
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#ifdef VIRTUAL
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void *start_timer(void *arg);
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#endif
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int stopStateMachine();
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#endif
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#ifdef MYTHEN3D
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#if defined(MYTHEN3D) || defined(XILINX_CHIPTESTBOARDD)
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int softwareTrigger();
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#endif
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#if defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)
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int softwareTrigger(int block);
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#endif
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#if defined(EIGERD) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD)
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#if defined(EIGERD) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || \
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defined(XILINX_CHIPTESTBOARDD)
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int startReadOut();
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#endif
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enum runStatus getRunStatus();
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#ifdef EIGERD
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void waitForAcquisitionEnd(int *ret, char *mess);
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#else
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#ifndef XILINX_CHIPTESTBOARDD
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void waitForAcquisitionEnd();
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#endif
|
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#endif
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#if defined(CHIPTESTBOARDD)
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int validateUDPSocket();
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void readandSendUDPFrames();
|
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@ -729,7 +748,8 @@ int readFrameFromFifo();
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#endif
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||||
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#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
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defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
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defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D) || \
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defined(XILINX_CHIPTESTBOARDD)
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u_int32_t runBusy();
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#endif
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@ -738,15 +758,11 @@ u_int32_t runState(enum TLogLevel lev);
|
||||
#endif
|
||||
|
||||
// common
|
||||
#ifndef XILINX_CHIPTESTBOARDD
|
||||
int calculateDataBytes();
|
||||
int getTotalNumberOfChannels();
|
||||
#endif
|
||||
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
|
||||
void getNumberOfChannels(int *nchanx, int *nchany);
|
||||
#endif
|
||||
#ifndef XILINX_CHIPTESTBOARDD
|
||||
int getNumberOfChips();
|
||||
int getNumberOfDACs();
|
||||
int getNumberOfChannelsPerChip();
|
||||
#endif
|
||||
int getNumberOfChannelsPerChip();
|
||||
@ -329,3 +329,4 @@ int getColumn();
|
||||
int setColumn(int);
|
||||
int get_pedestal_mode(int);
|
||||
int set_pedestal_mode(int);
|
||||
int config_transceiver(int);
|
||||
|
||||
@ -13,35 +13,54 @@
|
||||
#define LTC2620_D_MAX_STEPS (LTC2620_D_MAX_DAC_VAL + 1)
|
||||
|
||||
// defines from the fpga
|
||||
int LTC2620_D_HardMinVoltage = 0;
|
||||
int LTC2620_D_HardMaxVoltage = 0;
|
||||
char LTC2620_D_DriverFileName[MAX_STR_LENGTH];
|
||||
char LTC2620_D_PowerDownDriverFileName[MAX_STR_LENGTH];
|
||||
int LTC2620_D_NumDacs = 0;
|
||||
int LTC2620_D_NumDevices = 0;
|
||||
int LTC2620_D_NumChannelsPerDevice = 0;
|
||||
int LTC2620_D_DacDriverStartingDeviceIndex = 0;
|
||||
|
||||
void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs) {
|
||||
void LTC2620_D_SetDefines(int hardMinV, int hardMaxV, char *driverfname,
|
||||
int numdacs, int numdevices, int startingDeviceIndex,
|
||||
char *powerdownDriverfname) {
|
||||
LOG(logINFOBLUE,
|
||||
("Configuring DACs (LTC2620) to %s (numdacs:%d, hard max: %dmV)\n",
|
||||
driverfname, numdacs, hardMaxV));
|
||||
("Configuring DACs (LTC2620) to %s\n\t (numdacs:%d, hard min:%d, hard "
|
||||
"max: %dmV, idev:%d)\n",
|
||||
driverfname, numdacs, hardMinV, hardMaxV, startingDeviceIndex));
|
||||
LTC2620_D_HardMinVoltage = hardMinV;
|
||||
LTC2620_D_HardMaxVoltage = hardMaxV;
|
||||
memset(LTC2620_D_DriverFileName, 0, MAX_STR_LENGTH);
|
||||
strcpy(LTC2620_D_DriverFileName, driverfname);
|
||||
memset(LTC2620_D_PowerDownDriverFileName, 0, MAX_STR_LENGTH);
|
||||
strcpy(LTC2620_D_PowerDownDriverFileName, powerdownDriverfname);
|
||||
LTC2620_D_NumDacs = numdacs;
|
||||
LTC2620_D_NumDevices = numdevices;
|
||||
LTC2620_D_NumChannelsPerDevice = LTC2620_D_NumDacs / LTC2620_D_NumDevices;
|
||||
LTC2620_D_DacDriverStartingDeviceIndex = startingDeviceIndex;
|
||||
}
|
||||
|
||||
int LTC2620_D_GetMaxNumSteps() { return LTC2620_D_MAX_STEPS; }
|
||||
|
||||
int LTC2620_D_GetPowerDownValue() { return LTC2620_D_PWR_DOWN_VAL; }
|
||||
|
||||
int LTC2620_D_VoltageToDac(int voltage, int *dacval) {
|
||||
return ConvertToDifferentRange(0, LTC2620_D_HardMaxVoltage, 0,
|
||||
return ConvertToDifferentRange(LTC2620_D_HardMinVoltage,
|
||||
LTC2620_D_HardMaxVoltage, 0,
|
||||
LTC2620_D_MAX_DAC_VAL, voltage, dacval);
|
||||
}
|
||||
|
||||
int LTC2620_D_DacToVoltage(int dacval, int *voltage) {
|
||||
return ConvertToDifferentRange(0, LTC2620_D_MAX_DAC_VAL, 0,
|
||||
return ConvertToDifferentRange(0, LTC2620_D_MAX_DAC_VAL,
|
||||
LTC2620_D_HardMinVoltage,
|
||||
LTC2620_D_HardMaxVoltage, dacval, voltage);
|
||||
}
|
||||
|
||||
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
|
||||
int *dacval) {
|
||||
LOG(logDEBUG1, ("dacnum:%d, val:%d, ismV:%d\n", dacnum, val, mV));
|
||||
|
||||
// validate index
|
||||
if (dacnum < 0 || dacnum >= LTC2620_D_NumDacs) {
|
||||
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum,
|
||||
@ -49,53 +68,90 @@ int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
// get
|
||||
// validate set
|
||||
if (val < 0 && val != LTC2620_D_PWR_DOWN_VAL)
|
||||
return FAIL;
|
||||
|
||||
// convert to dac or get mV value
|
||||
*dacval = val;
|
||||
int dacmV = val;
|
||||
int ret = OK;
|
||||
if (mV) {
|
||||
ret = LTC2620_D_VoltageToDac(val, dacval);
|
||||
} else if (val >= 0) {
|
||||
// do not convert power down dac val
|
||||
ret = LTC2620_D_DacToVoltage(val, &dacmV);
|
||||
}
|
||||
|
||||
// conversion out of bounds
|
||||
if (ret == FAIL) {
|
||||
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum,
|
||||
(mV ? "mV" : "dac units")));
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
// set
|
||||
if ((*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
|
||||
LOG(logINFO, ("Setting DAC %2d [%-12s] : %d dac (%d mV)\n", dacnum,
|
||||
dacname, *dacval, dacmV));
|
||||
|
||||
*dacval = val;
|
||||
#ifndef VIRTUAL
|
||||
char fname[MAX_STR_LENGTH];
|
||||
strcpy(fname, LTC2620_D_DriverFileName);
|
||||
char temp[20];
|
||||
memset(temp, 0, sizeof(temp));
|
||||
sprintf(temp, "%d", dacnum);
|
||||
strcat(fname, temp);
|
||||
LOG(logDEBUG1, ("fname %s\n", fname));
|
||||
char fnameFormat[MAX_STR_LENGTH];
|
||||
memset(fnameFormat, 0, MAX_STR_LENGTH);
|
||||
strcpy(fnameFormat, LTC2620_D_DriverFileName);
|
||||
#endif
|
||||
|
||||
// open file
|
||||
FILE *fd = fopen(fname, "w");
|
||||
if (fd == NULL) {
|
||||
LOG(logERROR, ("Could not open file %s for writing to set dac %d\n",
|
||||
fname, dacnum));
|
||||
return FAIL;
|
||||
}
|
||||
// convert to string, add 0 and write to file
|
||||
fprintf(fd, "%d\n", *dacval);
|
||||
fclose(fd);
|
||||
// power down dac (different file name)
|
||||
if (val == LTC2620_D_PWR_DOWN_VAL) {
|
||||
#if defined(XILINX_CHIPTESTBOARDD) && !defined(VIRTUAL)
|
||||
LOG(logINFO, ("Powering down DAC %2d [%-6s] \n", dacnum, dacname));
|
||||
strcpy(fnameFormat, LTC2620_D_PowerDownDriverFileName);
|
||||
#endif
|
||||
}
|
||||
|
||||
// proper value to set
|
||||
else {
|
||||
// convert to dac or get mV value
|
||||
int dacmV = val;
|
||||
if (mV) {
|
||||
ret = LTC2620_D_VoltageToDac(val, dacval);
|
||||
} else if (val >= 0) {
|
||||
// do not convert power down dac val
|
||||
ret = LTC2620_D_DacToVoltage(val, &dacmV);
|
||||
}
|
||||
|
||||
// conversion out of bounds
|
||||
if (ret == FAIL) {
|
||||
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum,
|
||||
(mV ? "mV" : "dac units")));
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
// print and set
|
||||
#ifdef XILINX_CHIPTESTBOARDD
|
||||
if (*dacval >= 0) {
|
||||
LOG(logINFO, ("Setting DAC %2d [%-6s] : %d dac (%d mV)\n", dacnum,
|
||||
dacname, *dacval, dacmV));
|
||||
}
|
||||
#else
|
||||
if ((*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
|
||||
LOG(logINFO, ("Setting DAC %2d [%-12s] : %d dac (%d mV)\n", dacnum,
|
||||
dacname, *dacval, dacmV));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// set in file
|
||||
#ifndef VIRTUAL
|
||||
char fname[MAX_STR_LENGTH];
|
||||
memset(fname, 0, MAX_STR_LENGTH);
|
||||
#ifdef XILINX_CHIPTESTBOARDD
|
||||
int idev = LTC2620_D_DacDriverStartingDeviceIndex +
|
||||
(dacnum / LTC2620_D_NumChannelsPerDevice);
|
||||
int idac = dacnum % LTC2620_D_NumChannelsPerDevice;
|
||||
sprintf(fname, fnameFormat, idev, idac);
|
||||
#else
|
||||
sprintf(fname, "%s%d", fnameFormat, dacnum);
|
||||
#endif
|
||||
LOG(logDEBUG1, ("fname %s\n", fname));
|
||||
|
||||
// open file
|
||||
FILE *fd = fopen(fname, "w");
|
||||
if (fd == NULL) {
|
||||
LOG(logERROR, ("Could not open file %s for writing to set dac %d\n",
|
||||
fname, dacnum));
|
||||
return FAIL;
|
||||
}
|
||||
// convert to string, add 0 and write to file
|
||||
#ifdef XILINX_CHIPTESTBOARDD
|
||||
// not changing *dacval from -100 (cant write -100 to file: invalid arg)
|
||||
int writeValue = *dacval;
|
||||
if (writeValue == LTC2620_D_PWR_DOWN_VAL)
|
||||
writeValue = 1;
|
||||
fprintf(fd, "%d\n", writeValue);
|
||||
#else
|
||||
fprintf(fd, "%d\n", *dacval);
|
||||
#endif
|
||||
fclose(fd);
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -11,10 +11,13 @@
|
||||
#include <sys/mman.h> // mmap
|
||||
|
||||
/* global variables */
|
||||
#define CSP0 (0xB0010000)
|
||||
#define MEM_SIZE 0x100000
|
||||
|
||||
#define CSP0 (0xB0080000)
|
||||
#define CSP1 (0xB0050000) // udp
|
||||
#define MEM_SIZE (0x10000)
|
||||
//#define MEM_SIZE_CSP0 (4096)
|
||||
//#define MEM_SIZE_CSP1 (2 * 4096)
|
||||
u_int32_t *csp0base = 0;
|
||||
u_int32_t *csp1base = 0;
|
||||
|
||||
void bus_w(u_int32_t offset, u_int32_t data) {
|
||||
volatile u_int32_t *ptr1;
|
||||
@ -39,35 +42,53 @@ void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
|
||||
bus_w(aMSB, (value >> 32) & (0xffffffff));
|
||||
}
|
||||
|
||||
u_int32_t readRegister(u_int32_t offset) { return bus_r(offset); }
|
||||
|
||||
u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
|
||||
bus_w(offset, data);
|
||||
return readRegister(offset);
|
||||
}
|
||||
|
||||
int mapCSP0(void) {
|
||||
// if not mapped
|
||||
if (csp0base == 0) {
|
||||
LOG(logINFO, ("Mapping memory\n"));
|
||||
u_int32_t csps[2] = {CSP0, CSP1};
|
||||
u_int32_t **cspbases[2] = {&csp0base, &csp1base};
|
||||
char names[2][10] = {"csp0base", "csp1base"};
|
||||
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
// if not mapped
|
||||
if (*cspbases[i] == 0) {
|
||||
LOG(logINFO, ("Mapping memory for %s\n", names[i]));
|
||||
#ifdef VIRTUAL
|
||||
csp0base = malloc(MEM_SIZE);
|
||||
if (csp0base == NULL) {
|
||||
LOG(logERROR, ("Could not allocate virtual memory.\n"));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("memory allocated\n"));
|
||||
*cspbases[i] = malloc(MEM_SIZE);
|
||||
if (*cspbases[i] == NULL) {
|
||||
LOG(logERROR,
|
||||
("Could not allocate virtual memory for %s.\n", names[i]));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("memory allocated for %s\n", names[i]));
|
||||
#else
|
||||
int fd;
|
||||
fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
|
||||
if (fd == -1) {
|
||||
LOG(logERROR, ("Can't find /dev/mem\n"));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logDEBUG1, ("/dev/mem opened\n"));
|
||||
csp0base = (u_int32_t *)mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
|
||||
MAP_FILE | MAP_SHARED, fd, CSP0);
|
||||
if (csp0base == MAP_FAILED) {
|
||||
LOG(logERROR, ("Can't map memmory area\n"));
|
||||
return FAIL;
|
||||
}
|
||||
int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
|
||||
if (fd == -1) {
|
||||
LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logDEBUG1,
|
||||
("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
|
||||
*cspbases[i] =
|
||||
(u_int32_t *)mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
|
||||
MAP_FILE | MAP_SHARED, fd, csps[i]);
|
||||
if (*cspbases[i] == MAP_FAILED) {
|
||||
LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
|
||||
return FAIL;
|
||||
}
|
||||
#endif
|
||||
LOG(logINFO, ("csp0base mapped from %p to %p\n", csp0base,
|
||||
(csp0base + MEM_SIZE)));
|
||||
} else
|
||||
LOG(logINFO, ("Memory already mapped before\n"));
|
||||
LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n", names[i],
|
||||
*cspbases[i], *cspbases[i] + MEM_SIZE, csps[i]));
|
||||
// LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
|
||||
} else
|
||||
LOG(logINFO, ("Memory %s already mapped before\n", names[i]));
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
u_int32_t *Arm_getUDPBaseAddress() { return csp1base; }
|
||||
|
||||
@ -752,13 +752,17 @@ int readADCFromFile(char *fname, int *value) {
|
||||
|
||||
*value = -1;
|
||||
if (sscanf(line, "%d", value) != 1) {
|
||||
#ifdef XILINX_CHIPTESTBOARDD
|
||||
LOG(logERROR, ("Could not scan adc from %s\n", line));
|
||||
#else
|
||||
LOG(logERROR, ("Could not scan temperature from %s\n", line));
|
||||
#endif
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
#ifdef EIGERD
|
||||
*value /= 10;
|
||||
#else
|
||||
#elif !defined(XILINX_CHIPTESTBOARDD)
|
||||
LOG(logINFO, ("Temperature: %.2f °C\n", (double)(*value) / 1000.00));
|
||||
#endif
|
||||
|
||||
|
||||
@ -52,12 +52,26 @@ void initializePatternWord() {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CHIPTESTBOARDD) // TODO || defined(XILINX_CHIPTESTBOARDD)
|
||||
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
|
||||
uint64_t validate_readPatternIOControl() {
|
||||
#if defined(CHIPTESTBOARDD)
|
||||
return getU64BitReg(PATTERN_IO_CNTRL_LSB_REG, PATTERN_IO_CNTRL_MSB_REG);
|
||||
#elif defined(XILINX_CHIPTESTBOARDD)
|
||||
return (uint64_t)(bus_r(PINIOCTRLREG));
|
||||
#endif
|
||||
}
|
||||
|
||||
int validate_writePatternIOControl(char *message, uint64_t arg) {
|
||||
// validate input
|
||||
#ifdef XILINX_CHIPTESTBOARDD
|
||||
if (arg > BIT32_MSK) {
|
||||
strcpy(message, "Could not set pattern IO Control. Must be 32 bit for "
|
||||
"this detector\n");
|
||||
LOG(logERROR, (message));
|
||||
return FAIL;
|
||||
}
|
||||
#endif
|
||||
|
||||
writePatternIOControl(arg);
|
||||
|
||||
// validate result
|
||||
@ -77,9 +91,15 @@ int validate_writePatternIOControl(char *message, uint64_t arg) {
|
||||
}
|
||||
|
||||
void writePatternIOControl(uint64_t word) {
|
||||
#ifdef CHIPTESTBOARDD
|
||||
LOG(logINFO,
|
||||
("Setting Pattern I/O Control: 0x%llx\n", (long long int)word));
|
||||
setU64BitReg(word, PATTERN_IO_CNTRL_LSB_REG, PATTERN_IO_CNTRL_MSB_REG);
|
||||
#elif defined(XILINX_CHIPTESTBOARDD)
|
||||
uint32_t val = (uint32_t)word;
|
||||
LOG(logINFO, ("Setting Pattern I/O Control: 0x%x\n", val));
|
||||
bus_w(PINIOCTRLREG, val);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
196
slsDetectorServers/slsDetectorServer/src/programViaArm.c
Normal file
196
slsDetectorServers/slsDetectorServer/src/programViaArm.c
Normal file
@ -0,0 +1,196 @@
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-other
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
||||
#include "programViaArm.h"
|
||||
#include "clogger.h"
|
||||
#include "sls/sls_detector_defs.h"
|
||||
|
||||
#include <string.h> //memset
|
||||
#include <unistd.h> // access
|
||||
|
||||
#define CMD_ARM_LOAD_BIT_FILE \
|
||||
"~/fpgautil/fpgautil -b /root/apps/xilinx-ctb/XilinxCTB.bit -f Full"
|
||||
#define CMD_ARM_DEVICE_TREE_API_FOLDER \
|
||||
"/sys/kernel/config/device-tree/overlays/spidr"
|
||||
#define CMD_ARM_DEVICE_TREE_OVERLAY_FILE "/root/apps/xilinx-ctb/pl.dtbo"
|
||||
#define CMD_ARM_LOAD_DEVICE_TREE_FORMAT "cat %s > %s/dtbo"
|
||||
#define CMD_ARM_DEVICE_TREE_DST "/sys/bus/iio/devices/iio:device"
|
||||
#define CMD_ARM_DEVICE_NAME "xilinx-ams", "ad7689", "dac@0", "dac@1", "dac@2"
|
||||
#define TIME_LOAD_DEVICE_TREE_MS (500)
|
||||
|
||||
extern int executeCommand(char *command, char *result, enum TLogLevel level);
|
||||
|
||||
int resetFPGA(char *mess) {
|
||||
LOG(logINFOBLUE, ("Reseting FPGA...\n"));
|
||||
#ifndef VIRTUAL
|
||||
char retvals[MAX_STR_LENGTH] = {0};
|
||||
if (executeCommand(CMD_ARM_LOAD_BIT_FILE, retvals, logDEBUG1) == FAIL) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Could not reset fpga. Command to load bit file failed (%s)\n",
|
||||
retvals);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
#endif
|
||||
LOG(logINFOBLUE, ("FPGA reset successfully\n"))
|
||||
return OK;
|
||||
}
|
||||
|
||||
int loadDeviceTree(char *mess, int *adcDeviceIndex, int *dacDeviceIndex) {
|
||||
if (verifyDeviceTree(mess, adcDeviceIndex, dacDeviceIndex) == OK)
|
||||
return OK;
|
||||
|
||||
if (checksBeforeCreatingDeviceTree(mess) == FAIL)
|
||||
return FAIL;
|
||||
|
||||
if (createDeviceTree(mess) == FAIL)
|
||||
return FAIL;
|
||||
|
||||
if (verifyDeviceTree(mess, adcDeviceIndex, dacDeviceIndex) == FAIL) {
|
||||
LOG(logERROR, ("Device tree loading failed at verification\n"));
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
LOG(logINFOBLUE, ("Device tree loaded successfully\n"))
|
||||
return OK;
|
||||
}
|
||||
|
||||
int checksBeforeCreatingDeviceTree(char *mess) {
|
||||
// check if device tree overlay file exists
|
||||
if (access(CMD_ARM_DEVICE_TREE_OVERLAY_FILE, F_OK) != 0) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Device tree overlay file (%s) does not exist\n",
|
||||
CMD_ARM_DEVICE_TREE_OVERLAY_FILE);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("\tDevice tree overlay file exists (%s)\n",
|
||||
CMD_ARM_DEVICE_TREE_OVERLAY_FILE));
|
||||
|
||||
// check if device tree folder exists. If it does, remove it
|
||||
if (access(CMD_ARM_DEVICE_TREE_API_FOLDER, F_OK) == 0) {
|
||||
// remove it
|
||||
char cmd[MAX_STR_LENGTH] = {0};
|
||||
memset(cmd, 0, MAX_STR_LENGTH);
|
||||
sprintf(cmd, "rmdir %s", CMD_ARM_DEVICE_TREE_API_FOLDER);
|
||||
char retvals[MAX_STR_LENGTH] = {0};
|
||||
memset(retvals, 0, MAX_STR_LENGTH);
|
||||
if (executeCommand(cmd, retvals, logDEBUG1) == FAIL) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Could not unload device tree overlay api with %s (%s)\n",
|
||||
cmd, retvals);
|
||||
LOG(logWARNING, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("\tUnloaded existing device tree overlay api (%s)\n",
|
||||
CMD_ARM_DEVICE_TREE_API_FOLDER));
|
||||
} else {
|
||||
LOG(logINFO, ("\tNo existing device tree overlay api found(%s)\n",
|
||||
CMD_ARM_DEVICE_TREE_API_FOLDER));
|
||||
}
|
||||
|
||||
// create device tree overlay folder
|
||||
{
|
||||
char cmd[MAX_STR_LENGTH] = {0};
|
||||
memset(cmd, 0, MAX_STR_LENGTH);
|
||||
sprintf(cmd, "mkdir %s", CMD_ARM_DEVICE_TREE_API_FOLDER);
|
||||
char retvals[MAX_STR_LENGTH] = {0};
|
||||
memset(retvals, 0, MAX_STR_LENGTH);
|
||||
if (executeCommand(cmd, retvals, logDEBUG1) == FAIL) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Could not create device tree overlay api with %s (%s)\n",
|
||||
cmd, retvals);
|
||||
LOG(logWARNING, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("\tDevice tree overlay api created (%s)\n",
|
||||
CMD_ARM_DEVICE_TREE_API_FOLDER));
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
int createDeviceTree(char *mess) {
|
||||
char cmd[MAX_STR_LENGTH] = {0};
|
||||
memset(cmd, 0, MAX_STR_LENGTH);
|
||||
sprintf(cmd, CMD_ARM_LOAD_DEVICE_TREE_FORMAT,
|
||||
CMD_ARM_DEVICE_TREE_OVERLAY_FILE, CMD_ARM_DEVICE_TREE_API_FOLDER);
|
||||
char retvals[MAX_STR_LENGTH] = {0};
|
||||
memset(retvals, 0, MAX_STR_LENGTH);
|
||||
if (executeCommand(cmd, retvals, logDEBUG1) == FAIL) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Could not load device tree overlay with %s (%s)\n", cmd,
|
||||
retvals);
|
||||
LOG(logWARNING, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFO, ("\tDevice tree overlay created (cmd: %s)\n", cmd));
|
||||
|
||||
usleep(TIME_LOAD_DEVICE_TREE_MS * 1000);
|
||||
return OK;
|
||||
}
|
||||
|
||||
int verifyDeviceTree(char *mess, int *adcDeviceIndex, int *dacDeviceIndex) {
|
||||
LOG(logINFOBLUE, ("Verifying Device Tree...\n"));
|
||||
*adcDeviceIndex = 1;
|
||||
*dacDeviceIndex = 2;
|
||||
#ifndef VIRTUAL
|
||||
|
||||
// check if iio:device0-4 exists in device tree destination
|
||||
int hardcodedDeviceIndex = 0;
|
||||
for (int i = 0; i != 5; ++i) {
|
||||
char deviceName[MAX_STR_LENGTH] = {0};
|
||||
memset(deviceName, 0, MAX_STR_LENGTH);
|
||||
sprintf(deviceName, "%s%d/name", CMD_ARM_DEVICE_TREE_DST, i);
|
||||
// check if device exist
|
||||
if (access(deviceName, F_OK) != 0) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Could not verify device tree. Device %s does not exist\n",
|
||||
deviceName);
|
||||
LOG(logWARNING, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
// find name
|
||||
char cmd[MAX_STR_LENGTH] = {0};
|
||||
memset(cmd, 0, MAX_STR_LENGTH);
|
||||
sprintf(cmd, "cat %s", deviceName);
|
||||
char retvals[MAX_STR_LENGTH] = {0};
|
||||
memset(retvals, 0, MAX_STR_LENGTH);
|
||||
if (executeCommand(cmd, retvals, logDEBUG1) == FAIL) {
|
||||
snprintf(mess, MAX_STR_LENGTH,
|
||||
"Could not retrieve device name from device %s (%s)\n",
|
||||
deviceName, retvals);
|
||||
LOG(logWARNING, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
// verify name
|
||||
char *deviceNames[] = {CMD_ARM_DEVICE_NAME};
|
||||
if (strstr(retvals, deviceNames[hardcodedDeviceIndex]) == NULL) {
|
||||
// dacs got loaded first
|
||||
if (i == 1 &&
|
||||
strstr(retvals, deviceNames[hardcodedDeviceIndex + 1]) !=
|
||||
NULL) {
|
||||
++hardcodedDeviceIndex;
|
||||
*adcDeviceIndex = 4;
|
||||
*dacDeviceIndex = 1;
|
||||
} else {
|
||||
snprintf(
|
||||
mess, MAX_STR_LENGTH,
|
||||
"Could not verify device tree. Device %s expected %s but "
|
||||
"got %s\n",
|
||||
deviceName, deviceNames[i], retvals);
|
||||
LOG(logWARNING, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
}
|
||||
++hardcodedDeviceIndex;
|
||||
// in case dacs were loaded first
|
||||
if (hardcodedDeviceIndex == 5)
|
||||
hardcodedDeviceIndex = 1;
|
||||
}
|
||||
#endif
|
||||
LOG(logINFOBLUE, ("Device tree verified successfully [temp: 0, adc:%d, "
|
||||
"dac:%d, %d, %d]\n",
|
||||
*adcDeviceIndex, *dacDeviceIndex, *dacDeviceIndex + 1,
|
||||
*dacDeviceIndex + 2));
|
||||
return OK;
|
||||
}
|
||||
@ -79,7 +79,7 @@ int main(int argc, char *argv[]) {
|
||||
"\t-v, --version : Software version\n"
|
||||
"\t-p, --port <port> : TCP communication port with client. "
|
||||
"\n"
|
||||
"\t-g, --nomodule : [Mythen3][Gotthard2] \n"
|
||||
"\t-g, --nomodule : [Mythen3][Gotthard2][Xilinx Ctb] \n"
|
||||
"\t Generic or No Module mode. Skips "
|
||||
"detector type checks. \n"
|
||||
"\t-f, --phaseshift <value> : [Gotthard] only. Sets phase shift. \n"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -9,7 +9,10 @@ add_executable(xilinx_ctbDetectorServer_virtual
|
||||
../slsDetectorServer/src/common.c
|
||||
../slsDetectorServer/src/sharedMemory.c
|
||||
../slsDetectorServer/src/loadPattern.c
|
||||
../slsDetectorServer/src/programViaArm.c
|
||||
../slsDetectorServer/src/communication_funcs_UDP.c
|
||||
../../slsSupportLib/src/md5.c
|
||||
../slsDetectorServer/src/LTC2620_Driver.c
|
||||
)
|
||||
|
||||
include_directories(
|
||||
@ -23,11 +26,11 @@ target_include_directories(xilinx_ctbDetectorServer_virtual
|
||||
)
|
||||
|
||||
target_compile_definitions(xilinx_ctbDetectorServer_virtual
|
||||
PUBLIC XILINX_CHIPTESTBOARDD ARMPROCESSOR VIRTUAL STOP_SERVER
|
||||
PUBLIC XILINX_CHIPTESTBOARDD ARMPROCESSOR VIRTUAL STOP_SERVER
|
||||
)
|
||||
|
||||
target_link_libraries(xilinx_ctbDetectorServer_virtual
|
||||
PUBLIC pthread rt slsProjectCSettings
|
||||
PUBLIC pthread rt m slsProjectCSettings
|
||||
)
|
||||
|
||||
set_target_properties(xilinx_ctbDetectorServer_virtual PROPERTIES
|
||||
|
||||
@ -18,7 +18,7 @@ DESTDIR ?= bin
|
||||
INSTMODE = 0777
|
||||
|
||||
SRCS = slsDetectorFunctionList.c
|
||||
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c
|
||||
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c
|
||||
|
||||
OBJS = $(SRCS:.c=.o)
|
||||
|
||||
|
||||
@ -2,28 +2,48 @@
|
||||
// Copyright (C) 2021 Contributors to the SLS Detector Package
|
||||
#pragma once
|
||||
|
||||
#define CTRLREG1 (0x0)
|
||||
#define CTRL_REG (0x0)
|
||||
|
||||
#define CTRLREG2 (0x4)
|
||||
#define POWER_VIO_OFST (0)
|
||||
#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST)
|
||||
#define POWER_VCC_A_OFST (1)
|
||||
#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST)
|
||||
#define POWER_VCC_B_OFST (2)
|
||||
#define POWER_VCC_B_MSK (0x00000001 << POWER_VCC_B_OFST)
|
||||
#define POWER_VCC_C_OFST (3)
|
||||
#define POWER_VCC_C_MSK (0x00000001 << POWER_VCC_C_OFST)
|
||||
#define POWER_VCC_D_OFST (4)
|
||||
#define POWER_VCC_D_MSK (0x00000001 << POWER_VCC_D_OFST)
|
||||
|
||||
#define EMPTY4REG (0x4)
|
||||
|
||||
#define STATUSREG1 (0x8)
|
||||
|
||||
#define TRANSMISSIONBUSY_OFST (0)
|
||||
#define TRANSMISSIONBUSY_MSK (0x00000001 << TRANSMISSIONBUSY_OFST)
|
||||
|
||||
#define STATUSREG2 (0xC)
|
||||
|
||||
#define FPGAVERSIONREG (0x10)
|
||||
|
||||
#define COMPDATE_OFST (0)
|
||||
#define COMPDATE_MSK (0x00ffffff << COMPDATE_OFST)
|
||||
#define DETTYPE_OFST (24)
|
||||
#define DETTYPE_MSK (0x000000ff << DETTYPE_OFST)
|
||||
#define FPGACOMPDATE_OFST (0)
|
||||
#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST)
|
||||
#define FPGADETTYPE_OFST (24)
|
||||
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
|
||||
|
||||
#define EMPTY14REG (0x14)
|
||||
|
||||
#define EMPTY18REG (0x18)
|
||||
#define FIXEDPATTERNREG (0x18)
|
||||
#define FIXEDPATTERNVAL (0xACDC2016)
|
||||
|
||||
#define EMPTY1CREG (0x1C)
|
||||
|
||||
#define EMPTY20REG (0x20)
|
||||
#define APIVERSIONREG (0x20)
|
||||
|
||||
#define APICOMPDATE_OFST (0)
|
||||
#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST)
|
||||
#define APIDETTYPE_OFST (24)
|
||||
#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST)
|
||||
|
||||
#define EMPTY24REG (0x24)
|
||||
|
||||
@ -112,75 +132,75 @@
|
||||
|
||||
#define EMPTY9CREG (0x9C)
|
||||
|
||||
#define FLOWSTATUSREG (0x100)
|
||||
#define FLOW_STATUS_REG (0x100)
|
||||
|
||||
#define RSMBUSY_OFST (0)
|
||||
#define RSMBUSY_MSK (0x00000001 << RSMBUSY_OFST)
|
||||
#define RSMTRGWAIT_OFST (3)
|
||||
#define RSMTRGWAIT_MSK (0x00000001 << RSMTRGWAIT_OFST)
|
||||
#define CSMBUSY_OFST (17)
|
||||
#define CSMBUSY_MSK (0x00000001 << CSMBUSY_OFST)
|
||||
#define RSM_BUSY_OFST (0)
|
||||
#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST)
|
||||
#define RSM_TRG_WAIT_OFST (3)
|
||||
#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST)
|
||||
#define CSM_BUSY_OFST (17)
|
||||
#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST)
|
||||
|
||||
#define EMPTY104REG (0x104)
|
||||
|
||||
#define FLOWCONTROLREG (0x108)
|
||||
#define FLOW_CONTROL_REG (0x108)
|
||||
|
||||
#define STARTF_OFST (0)
|
||||
#define STARTF_MSK (0x00000001 << STARTF_OFST)
|
||||
#define STOPF_OFST (1)
|
||||
#define STOPF_MSK (0x00000001 << STOPF_OFST)
|
||||
#define RSTF_OFST (2)
|
||||
#define RSTF_MSK (0x00000001 << RSTF_OFST)
|
||||
#define SWTRIGGERF_OFST (3)
|
||||
#define SWTRIGGERF_MSK (0x00000001 << SWTRIGGERF_OFST)
|
||||
#define TRIGGERENABLE_OFST (4)
|
||||
#define TRIGGERENABLE_MSK (0x00000001 << TRIGGERENABLE_OFST)
|
||||
#define START_F_OFST (0)
|
||||
#define START_F_MSK (0x00000001 << START_F_OFST)
|
||||
#define STOP_F_OFST (1)
|
||||
#define STOP_F_MSK (0x00000001 << STOP_F_OFST)
|
||||
#define RST_F_OFST (2)
|
||||
#define RST_F_MSK (0x00000001 << RST_F_OFST)
|
||||
#define SW_TRIGGER_F_OFST (3)
|
||||
#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST)
|
||||
#define TRIGGER_ENABLE_OFST (4)
|
||||
#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST)
|
||||
|
||||
#define EMPTY10CREG (0x10C)
|
||||
|
||||
#define TIMEFROMSTARTOUTREG1 (0x110)
|
||||
#define TIME_FROM_START_OUT_REG_1 (0x110)
|
||||
|
||||
#define TIMEFROMSTARTOUTREG2 (0x114)
|
||||
#define TIME_FROM_START_OUT_REG_2 (0x114)
|
||||
|
||||
#define FRAMESFROMSTARTOUTREG1 (0x118)
|
||||
#define FRAMES_FROM_START_OUT_REG_1 (0x118)
|
||||
|
||||
#define FRAMESFROMSTARTOUTREG2 (0x11C)
|
||||
#define FRAMES_FROM_START_OUT_REG_2 (0x11C)
|
||||
|
||||
#define FRAMETIMEOUTREG1 (0x120)
|
||||
#define FRAME_TIME_OUT_REG_1 (0x120)
|
||||
|
||||
#define FRAMETIMEOUTREG2 (0x124)
|
||||
#define FRAME_TIME_OUT_REG_2 (0x124)
|
||||
|
||||
#define DELAYOUTREG1 (0x128)
|
||||
#define DELAY_OUT_REG_1 (0x128)
|
||||
|
||||
#define DELAYOUTREG2 (0x12C)
|
||||
#define DELAY_OUT_REG_2 (0x12C)
|
||||
|
||||
#define CYCLESOUTREG1 (0x130)
|
||||
#define CYCLES_OUT_REG_1 (0x130)
|
||||
|
||||
#define CYCLESOUTREG2 (0x134)
|
||||
#define CYCLES_OUT_REG_2 (0x134)
|
||||
|
||||
#define FRAMESOUTREG1 (0x138)
|
||||
#define FRAMES_OUT_REG_1 (0x138)
|
||||
|
||||
#define FRAMESOUTREG2 (0x13C)
|
||||
#define FRAMES_OUT_REG_2 (0x13C)
|
||||
|
||||
#define PERIODOUTREG1 (0x140)
|
||||
#define PERIOD_OUT_REG_1 (0x140)
|
||||
|
||||
#define PERIODOUTREG2 (0x144)
|
||||
#define PERIOD_OUT_REG_2 (0x144)
|
||||
|
||||
#define DELAYINREG1 (0x148)
|
||||
#define DELAY_IN_REG_1 (0x148)
|
||||
|
||||
#define DELAYINREG2 (0x14C)
|
||||
#define DELAY_IN_REG_2 (0x14C)
|
||||
|
||||
#define CYCLESINREG1 (0x150)
|
||||
#define CYCLES_IN_REG_1 (0x150)
|
||||
|
||||
#define CYCLESINREG2 (0x154)
|
||||
#define CYCLES_IN_REG_2 (0x154)
|
||||
|
||||
#define FRAMESINREG1 (0x158)
|
||||
#define FRAMES_IN_REG_1 (0x158)
|
||||
|
||||
#define FRAMESINREG2 (0x15C)
|
||||
#define FRAMES_IN_REG_2 (0x15C)
|
||||
|
||||
#define PERIODINREG1 (0x160)
|
||||
#define PERIOD_IN_REG_1 (0x160)
|
||||
|
||||
#define PERIODINREG2 (0x164)
|
||||
#define PERIOD_IN_REG_2 (0x164)
|
||||
|
||||
#define EMPTY168REG (0x168)
|
||||
|
||||
@ -484,18 +504,15 @@
|
||||
|
||||
#define EMPTY3FCREG (0x3FC)
|
||||
|
||||
#define EXPCTRLREG (0x400)
|
||||
|
||||
#define STARTP_OFST (0)
|
||||
#define STARTP_MSK (0x00000001 << STARTP_OFST)
|
||||
#define EMPTY400REG (0x400)
|
||||
|
||||
#define EMPTY404REG (0x404)
|
||||
|
||||
#define EXPFRAMESREG (0x408)
|
||||
#define EMPTY408REG (0x408)
|
||||
|
||||
#define EMPTY40CREG (0x40C)
|
||||
|
||||
#define EXPTIMEREG (0x410)
|
||||
#define EMPTY410REG (0x410)
|
||||
|
||||
#define EMPTY414REG (0x414)
|
||||
|
||||
@ -615,47 +632,56 @@
|
||||
|
||||
#define EMPTY4FCREG (0x4FC)
|
||||
|
||||
#define FIFOTOGBCONTROLREG (0x500)
|
||||
#define FIFO_TO_GB_CONTROL_REG (0x500)
|
||||
|
||||
#define ENABLEDCHANNELS_OFST (0)
|
||||
#define ENABLEDCHANNELS_MSK (0x00001fff << ENABLEDCHANNELS_OFST)
|
||||
#define ROMODE_OFST (13)
|
||||
#define ROMODE_MSK (0x00000007 << ROMODE_OFST)
|
||||
#define COUNTFRAMESFROMUPDATE_OFST (16)
|
||||
#define COUNTFRAMESFROMUPDATE_MSK (0x00000001 << COUNTFRAMESFROMUPDATE_OFST)
|
||||
#define STARTSTREAMING_P_OFST (17)
|
||||
#define STARTSTREAMING_P_MSK (0x00000001 << STARTSTREAMING_P_OFST)
|
||||
#define ENABLED_CHANNELS_ADC_OFST (0)
|
||||
#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
|
||||
#define ENABLED_CHANNELS_D_OFST (8)
|
||||
#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST)
|
||||
#define ENABLED_CHANNELS_X_OFST (9)
|
||||
#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST)
|
||||
#define RO_MODE_ADC_OFST (13)
|
||||
#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST)
|
||||
#define RO_MODE_D_OFST (14)
|
||||
#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST)
|
||||
#define RO_MODE_X_OFST (15)
|
||||
#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST)
|
||||
#define COUNT_FRAMES_FROM_UPDATE_OFST (16)
|
||||
#define COUNT_FRAMES_FROM_UPDATE_MSK \
|
||||
(0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
|
||||
#define START_STREAMING_P_OFST (17)
|
||||
#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST)
|
||||
|
||||
#define EMPTY504REG (0x504)
|
||||
|
||||
#define NOSAMPLESDREG (0x508)
|
||||
#define NO_SAMPLES_D_REG (0x508)
|
||||
|
||||
#define NOSAMPLESD_OFST (0)
|
||||
#define NOSAMPLESD_MSK (0x00003fff << NOSAMPLESD_OFST)
|
||||
#define NO_SAMPLES_D_OFST (0)
|
||||
#define NO_SAMPLES_D_MSK (0x00003fff << NO_SAMPLES_D_OFST)
|
||||
|
||||
#define EMPTY50CREG (0x50C)
|
||||
|
||||
#define NOSAMPLESAREG (0x510)
|
||||
#define NO_SAMPLES_A_REG (0x510)
|
||||
|
||||
#define NOSAMPLESA_OFST (0)
|
||||
#define NOSAMPLESA_MSK (0x00003fff << NOSAMPLESA_OFST)
|
||||
#define NO_SAMPLES_A_OFST (0)
|
||||
#define NO_SAMPLES_A_MSK (0x00003fff << NO_SAMPLES_A_OFST)
|
||||
|
||||
#define EMPTY514REG (0x514)
|
||||
|
||||
#define NOSAMPLESXREG (0x518)
|
||||
#define NO_SAMPLES_X_REG (0x518)
|
||||
|
||||
#define NOSAMPLESX_OFST (0)
|
||||
#define NOSAMPLESX_MSK (0x00001fff << NOSAMPLESX_OFST)
|
||||
#define NO_SAMPLES_X_OFST (0)
|
||||
#define NO_SAMPLES_X_MSK (0x00001fff << NO_SAMPLES_X_OFST)
|
||||
|
||||
#define EMPTY51CREG (0x51C)
|
||||
|
||||
#define COUNTFRAMESFROMREG1 (0x520)
|
||||
#define COUNT_FRAMES_FROM_REG_1 (0x520)
|
||||
|
||||
#define COUNTFRAMESFROMREG2 (0x524)
|
||||
#define COUNT_FRAMES_FROM_REG_2 (0x524)
|
||||
|
||||
#define LOCALFRAMENUMBERREG1 (0x528)
|
||||
#define LOCAL_FRAME_NUMBER_REG_1 (0x528)
|
||||
|
||||
#define LOCALFRAMENUMBERREG2 (0x52C)
|
||||
#define LOCAL_FRAME_NUMBER_REG_2 (0x52C)
|
||||
|
||||
#define EMPTY530REG (0x530)
|
||||
|
||||
@ -697,51 +723,75 @@
|
||||
|
||||
#define EMPTY57CREG (0x57C)
|
||||
|
||||
#define EMPTY580REG (0x580)
|
||||
#define A_FIFO_OVERFLOW_STATUS_REG (0x580)
|
||||
|
||||
#define EMPTY584REG (0x584)
|
||||
|
||||
#define EMPTY588REG (0x588)
|
||||
#define A_FIFO_EMPTY_STATUS_REG (0x588)
|
||||
|
||||
#define EMPTY58CREG (0x58C)
|
||||
|
||||
#define EMPTY590REG (0x590)
|
||||
#define A_FIFO_FULL_STATUS_REG (0x590)
|
||||
|
||||
#define EMPTY594REG (0x594)
|
||||
|
||||
#define EMPTY598REG (0x598)
|
||||
#define D_FIFO_OVERFLOW_STATUS_REG (0x598)
|
||||
|
||||
#define D_FIFO_OVERFLOW_STATUS_OFST (0)
|
||||
#define D_FIFO_OVERFLOW_STATUS_MSK (0x00000001 << D_FIFO_OVERFLOW_STATUS_OFST)
|
||||
|
||||
#define EMPTY59CREG (0x59C)
|
||||
|
||||
#define EMPTY5A0REG (0x5A0)
|
||||
#define D_FIFO_EMPTY_STATUS_REG (0x5A0)
|
||||
|
||||
#define D_FIFO_EMPTY_STATUS_OFST (0)
|
||||
#define D_FIFO_EMPTY_STATUS_MSK (0x00000001 << D_FIFO_EMPTY_STATUS_OFST)
|
||||
|
||||
#define EMPTY5A4REG (0x5A4)
|
||||
|
||||
#define EMPTY5A8REG (0x5A8)
|
||||
#define D_FIFO_FULL_STATUS_REG (0x5A8)
|
||||
|
||||
#define D_FIFO_FULL_STATUS_OFST (0)
|
||||
#define D_FIFO_FULL_STATUS_MSK (0x00000001 << D_FIFO_FULL_STATUS_OFST)
|
||||
|
||||
#define EMPTY5ACREG (0x5AC)
|
||||
|
||||
#define EMPTY5B0REG (0x5B0)
|
||||
#define X_FIFO_OVERFLOW_STATUS_REG (0x5B0)
|
||||
|
||||
#define X_FIFO_OVERFLOW_STATUS_OFST (0)
|
||||
#define X_FIFO_OVERFLOW_STATUS_MSK (0x0000000f << X_FIFO_OVERFLOW_STATUS_OFST)
|
||||
|
||||
#define EMPTY5B4REG (0x5B4)
|
||||
|
||||
#define EMPTY5B8REG (0x5B8)
|
||||
#define X_FIFO_EMPTY_STATUS_REG (0x5B8)
|
||||
|
||||
#define X_FIFO_EMPTY_STATUS_OFST (0)
|
||||
#define X_FIFO_EMPTY_STATUS_MSK (0x0000000f << X_FIFO_EMPTY_STATUS_OFST)
|
||||
|
||||
#define EMPTY5BCREG (0x5BC)
|
||||
|
||||
#define EMPTY5C0REG (0x5C0)
|
||||
#define X_FIFO_FULL_STATUS_REG (0x5C0)
|
||||
|
||||
#define X_FIFO_FULL_STATUS_OFST (0)
|
||||
#define X_FIFO_FULL_STATUS_MSK (0x0000000f << X_FIFO_FULL_STATUS_OFST)
|
||||
|
||||
#define EMPTY5C4REG (0x5C4)
|
||||
|
||||
#define EMPTY5C8REG (0x5C8)
|
||||
#define A_FIFO_CLEAN_REG (0x5C8)
|
||||
|
||||
#define EMPTY5CCREG (0x5CC)
|
||||
|
||||
#define EMPTY5D0REG (0x5D0)
|
||||
#define D_FIFO_CLEAN_REG (0x5D0)
|
||||
|
||||
#define D_FIFO_CLEAN_OFST (0)
|
||||
#define D_FIFO_CLEAN_MSK (0x00000001 << D_FIFO_CLEAN_OFST)
|
||||
|
||||
#define EMPTY5D4REG (0x5D4)
|
||||
|
||||
#define EMPTY5D8REG (0x5D8)
|
||||
#define X_FIFO_CLEAN_REG (0x5D8)
|
||||
|
||||
#define X_FIFO_CLEAN_OFST (0)
|
||||
#define X_FIFO_CLEAN_MSK (0x0000000f << X_FIFO_CLEAN_OFST)
|
||||
|
||||
#define EMPTY5DCREG (0x5DC)
|
||||
|
||||
@ -777,6 +827,8 @@
|
||||
#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST)
|
||||
#define BUSY_OFST (4)
|
||||
#define BUSY_MSK (0x00000001 << BUSY_OFST)
|
||||
#define READOUTFROMASIC_OFST (5)
|
||||
#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST)
|
||||
|
||||
#define EMPTY60CREG (0x60C)
|
||||
|
||||
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -4,7 +4,7 @@
|
||||
#include "RegisterDefs.h"
|
||||
#include "sls/sls_detector_defs.h"
|
||||
|
||||
#define REQRD_FRMWRE_VRSN (0x230000)
|
||||
#define REQRD_FRMWRE_VRSN (0x230710)
|
||||
#define KERNEL_DATE_VRSN "Wed Nov 29 17:32:14 CET 2023"
|
||||
|
||||
#define LINKED_SERVER_NAME "xilinx_ctbDetectorServer"
|
||||
@ -12,16 +12,134 @@
|
||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NCHAN (1)
|
||||
#define NCHAN (40)
|
||||
#define NCHAN_ANALOG (32)
|
||||
#define NCHAN_DIGITAL (64)
|
||||
#define NCHAN_TRANSCEIVER (4)
|
||||
#define NBITS_PER_TRANSCEIVER (64)
|
||||
#define NCHIP (1)
|
||||
#define NDAC (24)
|
||||
#define NPWR (6)
|
||||
#define NDAC_ONLY (NDAC - NPWR)
|
||||
|
||||
enum ADCINDEX { V_PWR_IO };
|
||||
enum DACINDEX { D0 };
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
|
||||
|
||||
#define DAC_DRIVER_NUM_DEVICES (3)
|
||||
#define DAC_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device%d/out_voltage%d_raw")
|
||||
#define DAC_POWERDOWN_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device%d/out_voltage%d_powerdown")
|
||||
|
||||
#define SLOWADC_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device%d/in_voltage%d_raw")
|
||||
//#define SLOWDAC_CONVERTION_FACTOR_TO_UV (62.500953)
|
||||
|
||||
#define TEMP_DRIVER_FILE_NAME \
|
||||
("/sys/bus/iio/devices/iio:device0/in_temp7_input")
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_EXPTIME (0)
|
||||
#define DEFAULT_PERIOD (300 * 1000) // 300us
|
||||
#define DEFAULT_READOUT_MODE (TRANSCEIVER_ONLY)
|
||||
#define DEFAULT_READOUT_MODE_STR "transceiver_only"
|
||||
#define DEFAULT_TRANSCEIVER_MASK (0x3) // TODO: check
|
||||
#define DEFAULT_NUM_ASAMPLES (1)
|
||||
#define DEFAULT_NUM_DSAMPLES (1)
|
||||
#define DEFAULT_NUM_TSAMPLES (200)
|
||||
#define DEFAULT_STARTING_FRAME_NUMBER (1)
|
||||
#define DEFAULT_VLIMIT (-100)
|
||||
#define DEFAULT_DELAY (0)
|
||||
|
||||
#define MAX_TRANSCEIVER_MASK (0xF)
|
||||
#define MAX_TRANSCEIVER_SAMPLES (0x1FFF)
|
||||
|
||||
#define MAX_ANALOG_SAMPLES (0x3FFF)
|
||||
#define MAX_DIGITAL_SAMPLES (0x3FFF)
|
||||
|
||||
#define DAC_MIN_MV (0)
|
||||
#define DAC_MAX_MV (2500)
|
||||
|
||||
#define TICK_CLK (20) // MHz (trig_timeFromStart, frametime, timeFromStart)
|
||||
#define RUN_CLK \
|
||||
(100) // MHz (framesFromStart, c_swTrigger, run, waitForTrigger, starting,
|
||||
// acquiring, waitForPeriod, internalStop, c_framesFromSTart_reset,
|
||||
// s_start, c_stop, triggerEnable, period, frames, cycles, delay)
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_OUT_0US_TIMES (35000) // 2s
|
||||
|
||||
#define BIT32_MSK (0xFFFFFFFF)
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
#define MAX_DATA_SIZE_IN_PACKET (8144)
|
||||
|
||||
/* Enum Definitions */
|
||||
enum ADCINDEX {
|
||||
S_ADC0,
|
||||
S_ADC1,
|
||||
S_ADC2,
|
||||
S_ADC3,
|
||||
S_ADC4,
|
||||
S_ADC5,
|
||||
S_ADC6,
|
||||
S_ADC7,
|
||||
TEMP_FPGA
|
||||
};
|
||||
enum DACINDEX {
|
||||
D0,
|
||||
D1,
|
||||
D2,
|
||||
D3,
|
||||
D4,
|
||||
D5,
|
||||
D6,
|
||||
D7,
|
||||
D8,
|
||||
D9,
|
||||
D10,
|
||||
D11,
|
||||
D12,
|
||||
D13,
|
||||
D14,
|
||||
D15,
|
||||
D16,
|
||||
D17,
|
||||
D_PWR_D,
|
||||
D_PWR_EMPTY,
|
||||
D_PWR_IO,
|
||||
D_PWR_A,
|
||||
D_PWR_B,
|
||||
D_PWR_C
|
||||
};
|
||||
|
||||
/* Struct Definitions */
|
||||
typedef struct udp_header_struct {
|
||||
uint32_t udp_destmac_msb;
|
||||
uint16_t udp_srcmac_msb;
|
||||
uint16_t udp_destmac_lsb;
|
||||
uint32_t udp_srcmac_lsb;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl : 4, ip_ver : 4;
|
||||
uint16_t udp_ethertype;
|
||||
uint16_t ip_identification;
|
||||
uint16_t ip_totallength;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
|
||||
uint16_t ip_srcip_msb;
|
||||
uint16_t ip_checksum;
|
||||
uint16_t ip_destip_msb;
|
||||
uint16_t ip_srcip_lsb;
|
||||
uint16_t udp_srcport;
|
||||
uint16_t ip_destip_lsb;
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
} udp_header;
|
||||
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
|
||||
Reference in New Issue
Block a user