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Moench rewrite (#597)

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* copied jungfrau server to moench and adapted

* fixed image size and num packets

* read n rows allows 16

* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options

* moench:removing the decrement (which was in jf)  in read n rows to register

* removed lblsamples from gui
This commit is contained in:
Dhanya Thattil
2022-12-15 09:16:51 +01:00
committed by GitHub
parent 7ab3b25f87
commit 39b1f5bbf2
58 changed files with 4309 additions and 5499 deletions
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272
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
View File

@ -4,18 +4,147 @@
#include "RegisterDefs.h"
#include "sls/sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x221205
#define REQRD_FRMWRE_VRSN_BOARD2 0x221130 // 1.0 pcb (version = 010)
#define REQRD_FRMWRE_VRSN 0x221130 // 2.0 pcb (version = 011)
#define NUM_HARDWARE_VERSIONS (1)
#define NUM_HARDWARE_VERSIONS (2)
#define HARDWARE_VERSION_NUMBERS \
{ 0x1 }
{ 0x2, 0x3 }
#define HARDWARE_VERSION_NAMES \
{ "1.0" }
{ "1.0", "2.0" }
#define ID_FILE ("detid_moench.txt")
#define CONFIG_FILE ("config_moench.txt")
#define LINKED_SERVER_NAME "moenchDetectorServer"
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Hardware Definitions */
#define NCHAN (400 * 400)
#define NCHIP (1)
#define NDAC (8)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
#define CLK_RUN (40) // MHz
#define CLK_SYNC (20) // MHz
#define ADC_CLK_INDEX (1)
#define DBIT_CLK_INDEX (0)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (10 * 1000) // ns
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (GAIN0)
#define DEFAULT_GAINMODE (DYNAMIC)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define DEFAULT_STRG_CLL_STRT_CHIP11 (0x3)
#define DEFAULT_STRG_CLL_DLY (0)
#define DEFAULT_FLIP_ROWS (0)
#define DEFAULT_FILTER_RESISTOR (1) // higher resistor
#define DEFAULT_FILTER_CELL (0)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define MAX_FILTER_CELL_VAL (12)
#define READ_N_ROWS_MULTIPLE (16) // 400 rows/50packets * 2 interfaces
#define MIN_ROWS_PER_READOUT (16)
#define MAX_ROWS_PER_READOUT (400)
#define ROWS_PER_PACKET (8)
/* Defines in the Firmware */
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define MAX_STORAGE_CELL_VAL (15) // 0xF
#define MAX_STORAGE_CELL_CHIP11_VAL (3)
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define ACQ_TIME_MIN_CLOCK (2)
#define ASIC_FILTER_MAX_RES_VALUE (1)
#define MAX_SELECT_CHIP10_VAL (63)
#define MAX_PHASE_SHIFTS (240)
#define BIT16_MASK (0xFFFF)
#define GAIN_VAL_OFST (14)
#define GAIN_VAL_MSK (0x3 << GAIN_VAL_OFST)
// pipeline
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
// 2.0 pcb (chipv1.1)
#define SAMPLE_ADC_FULL_SPEED_CHIP11 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x0000
#define SAMPLE_ADC_HALF_SPEED_CHIP11 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1110
#define SAMPLE_ADC_QUARTER_SPEED_CHIP11 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2230
#define ADC_PHASE_FULL_SPEED_CHIP11 (160)
#define ADC_PHASE_HALF_SPEED_CHIP11 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP11 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP11 (80)
#define DBIT_PHASE_HALF_SPEED_CHIP11 (135)
#define DBIT_PHASE_QUARTER_SPEED_CHIP11 (135)
#define ADC_OFST_FULL_SPEED_VAL_CHIP11 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP11 (0x08)
#define ADC_OFST_QUARTER_SPEED_VAL_CHIP11 (0x04)
// 2.0 pcb (chipv1.0)
#define SAMPLE_ADC_FULL_SPEED_CHIP10 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x0100
#define SAMPLE_ADC_HALF_SPEED_CHIP10 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED_CHIP10 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define ADC_PHASE_FULL_SPEED_CHIP10 (160)
#define ADC_PHASE_HALF_SPEED_CHIP10 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP10 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP10 (125)
#define DBIT_PHASE_HALF_SPEED_CHIP10 (175)
#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (175)
#define ADC_OFST_FULL_SPEED_VAL_CHIP10 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP10 (0x08)
#define ADC_OFST_QUARTER_SPEED_VAL_CHIP10 (0x04)
// 1.0 pcb (2 resistor network)
#define SAMPLE_ADC_HALF_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1300
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2610
#define ADC_PHASE_HALF_SPEED_BOARD2 (110)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220)
#define DBIT_PHASE_HALF_SPEED_BOARD2 (150)
#define DBIT_PHASE_QUARTER_SPEED_BOARD2 (150)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x10)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x08)
/* Struct Definitions */
typedef struct udp_header_struct {
@ -45,111 +174,44 @@ typedef struct udp_header_struct {
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
MO_VBP_COLBUF,
MO_VIPRE,
MO_VIN_CM,
MO_VB_SDA,
MO_VCASC_SFP,
MO_VOUT_CM,
MO_VIPRE_CDS,
MO_IBIAS_SFP
J_VB_COMP,
J_VDD_PROT,
J_VIN_COM,
J_VREF_PRECH,
J_VB_PIXBUF,
J_VB_DS,
J_VREF_DS,
J_VREF_COMP
};
#define DAC_NAMES \
"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", \
"vipre_cds", "ibias_sfp"
"vb_comp", "vdd_prot", "vin_com", "vref_prech", "vb_pixbuf", "vb_ds", \
"vref_ds", "vref_comp"
#define DEFAULT_DAC_VALS \
{ \
1300, /* MO_VBP_COLBUF */ \
1000, /* MO_VIPRE */ \
1400, /* MO_VIN_CM */ \
680, /* MO_VB_SDA */ \
1428, /* MO_VCASC_SFP */ \
1200, /* MO_VOUT_CM */ \
800, /* MO_VIPRE_CDS */ \
900 /* MO_IBIAS_SFP */ \
1220, /* J_VB_COMP */ \
3000, /* J_VDD_PROT */ \
1053, /* J_VIN_COM */ \
1450, /* J_VREF_PRECH */ \
750, /* J_VB_PIXBUF */ \
1000, /* J_VB_DS */ \
480, /* J_VREF_DS */ \
420 /* J_VREF_COMP */ \
};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
#define MASTER_NAMES "hardware", "master", "slave"
/* Hardware Definitions */
#define NCHAN (32)
#define NCHIP (1)
#define NDAC (8)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define NSAMPLES_PER_ROW (25)
#define NCHANS_PER_ADC (25)
#define NUMSETTINGS (2)
#define NSPECIALDACS (3)
#define SPECIALDACINDEX {J_VREF_PRECH, J_VREF_DS, J_VREF_COMP};
#define SPECIAL_DEFAULT_DYNAMIC_GAIN_VALS \
{ 1450, 480, 420 }
#define SPECIAL_DEFAULT_DYNAMICHG0_GAIN_VALS \
{ 1550, 450, 620 }
/** Default Parameters */
#define DEFAULT_PATTERN_FILE ("DefaultPattern_moench.txt")
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (5000)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK_AT_STARTUP (200) // 40
#define DEFAULT_ADC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_SYNC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_DBIT_CLK_AT_STARTUP (200)
#define DEFAULT_RUN_CLK (40)
#define DEFAULT_ADC_CLK (20)
#define DEFAULT_DBIT_CLK (40)
#define DEFAULT_ADC_PHASE_DEG (30)
#define DEFAULT_PIPELINE (15)
#define DEFAULT_SETTINGS (G4_HIGHGAIN)
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
// settings
#define DEFAULT_PATMASK (0x00000C800000800AULL)
#define G1_HIGHGAIN_PATSETBIT (0x00000C0000008008ULL)
#define G1_LOWGAIN_PATSETBIT (0x0000040000008000ULL)
#define G2_HIGHCAP_HIGHGAIN_PATSETBIT (0x0000080000000008ULL)
#define G2_HIGHCAP_LOWGAIN_PATSETBIT (0x0000000000000000ULL)
#define G2_LOWCAP_HIGHGAIN_PATSETBIT (0x00000C800000800AULL)
#define G2_LOWCAP_LOWGAIN_PATSETBIT (0x0000048000008002ULL)
#define G4_HIGHGAIN_PATSETBIT (0x000008800000000AULL)
#define G4_LOWGAIN_PATSETBIT (0x0000008000000002ULL)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
/* Defines in the Firmware */
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define ADC_PORT_INVERT_VAL (0x4a342593)
#define MAXIMUM_ADC_CLK (20)
#define PLL_VCO_FREQ_MHZ (800)
enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "dbit"