mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 15:00:02 +02:00
modifying registers_m.h wrt Carlos firmware document, modified detector initialization in firmware_funcs.c and related files
This commit is contained in:
parent
15424149cd
commit
39a985cbba
@ -13,10 +13,6 @@
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//#define VERYVERBOSE
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#ifdef SHAREDMEMORY
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#include "sharedmemory.h"
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#endif
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#include <sys/ipc.h>
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#include <sys/shm.h>
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#include <sys/stat.h>
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@ -139,12 +135,6 @@ int mapCSP0(void) {
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#ifdef VIRTUAL
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CSP0BASE = malloc(MEM_SIZE);
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printf("memory allocated\n");
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#endif
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#ifdef SHAREDMEMORY
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if ( (res=inism(SMSV))<0) {
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printf("error attaching shared memory! %i",res);
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return FAIL;
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}
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#endif
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//printf("CSPObase is 0x%08x \n",CSP0BASE);
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printf("CSPOBASE mapped from %08x to %08x\n",CSP0BASE,CSP0BASE+MEM_SIZE);
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@ -201,39 +191,13 @@ int powerChip (int on){
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void initializeDetector(){
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printf("Initializing Detector\n");
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int i;
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//printf("Bus test... ");
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for (i=0; i<1000000; i++) {
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bus_w(SET_DELAY_LSB_REG, i*100);
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bus_r(FPGA_VERSION_REG);
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if (i*100!=bus_r(SET_DELAY_LSB_REG))
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cprintf(RED,"Bus Test ERROR: wrote 0x%x, read 0x%x\n",i*100,bus_r(SET_DELAY_LSB_REG));
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}
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//printf("Finished\n");
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//confirm the detector type
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if (((bus_r(PCB_REV_REG) & DETECTOR_TYPE_MASK)>>DETECTOR_TYPE_OFFSET) != JUNGFRAU_MODULE_ID){
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cprintf(BG_RED,"This is not a Jungfrau Server (enum:%d)\n",myDetectorType);
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//initial test
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if ( (testFpga() == FAIL) || (testBus() == FAIL) || (checkType() == FAIL)) { /*Check with Carlos if type check required */
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cprintf(BG_RED, "Dangerous to continue. Goodbye!\n");
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exit(-1);
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}
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cprintf(BLUE,"\n\n********************************************************\n"
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"*********************Jungfrau Server********************\n"
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"********************************************************\n");
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//print version
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cprintf(BLUE,"\n"
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"Firmware Version:\t 0x%x\n"
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"Software Version:\t %llx\n"
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//"F/w-S/w API Version:\t\t %lld\n"
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//"Required Firmware Version:\t %d\n"
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"Fixed Pattern:\t\t 0x%x\n"
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"Board Revision:\t\t 0x%x\n"
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"\n********************************************************\n",
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bus_r(FPGA_VERSION_REG),(long long unsigned int)(((int64_t)SVNREV <<32) | (int64_t)SVNDATE)
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//,sw_fw_apiversion, REQUIRED_FIRMWARE_VERSION
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,bus_r(FIX_PATT_REG),(bus_r(PCB_REV_REG)&BOARD_REVISION_MASK)
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);
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printVersions();
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printf("Resetting PLL\n");
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resetPLL();
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@ -242,9 +206,12 @@ void initializeDetector(){
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bus_w16(CONTROL_REG, GB10_RESET_BIT);
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bus_w16(CONTROL_REG, 0);
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//allocating module structure for the detector in the server
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#ifdef MCB_FUNCS
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initDetector();
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#endif
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/*some registers set, which is in common with jungfrau, please check */
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prepareADC();
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/*some registers set, which is in common with jungfrau, please check */
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@ -319,6 +286,32 @@ void initializeDetector(){
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}
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int checkType() {
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volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type != JUNGFRAU){
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cprintf(BG_RED,"This is not a Jungfrau Server (read %d, expected %d)\n",type, JUNGFRAU);
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return FAIL;
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}
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return OK;
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}
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void printVersions() {
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cprintf(BLUE,"\n\n"
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"********************************************************\n"
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"*********************Jungfrau Server********************\n"
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"********************************************************\n\n"
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"Firmware Version:\t 0x%llx\n"
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"Software Version:\t 0x%llx\n"
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//"F/w-S/w API Version:\t\t %lld\n"
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//"Required Firmware Version:\t %d\n"
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"********************************************************\n",
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(long long unsigned int)getId(DETECTOR_FIRMWARE_VERSION),
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(long long unsigned int)getId(DETECTOR_SOFTWARE_VERSION)
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//,(long long unsigned int)getId(SOFTWARE_FIRMWARE_API_VERSION)
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//REQUIRED_FIRMWARE_VERSION);
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);
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}
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u_int16_t bus_r16(u_int32_t offset){
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volatile u_int16_t *ptr1;
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@ -1052,79 +1045,88 @@ u_int64_t getDetectorNumber() {
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return res;
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}
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u_int32_t getFirmwareVersion() {
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return bus_r(FPGA_VERSION_REG);
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u_int64_t getFirmwareVersion() {
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return ((bus_r(FPGA_VERSION_REG) & BOARD_REVISION_MSK) >> BOARD_REVISION_OFST);
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}
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u_int32_t getFirmwareSVNVersion(){
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return bus_r(FPGA_SVN_REG);
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int64_t getId(enum idMode arg) {
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int64_t retval = -1;
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switch(arg){
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case DETECTOR_SERIAL_NUMBER:
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retval = getDetectorNumber();
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break;
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case DETECTOR_FIRMWARE_VERSION:
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retval=getFirmwareSVNVersion();
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retval=(retval <<32) | getFirmwareVersion();
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break;
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case DETECTOR_SOFTWARE_VERSION:
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retval= SVNREV;
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retval= (retval <<32) | SVNDATE;
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break;
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default:
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printf("Required unknown id %d \n", arg);
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break;
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}
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return retval;
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}
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// for fpga test
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int testFifos(void) {
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printf("Fifo test not implemented!\n");
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/*bus_w16(CONTROL_REG, START_FIFOTEST_BIT); check with Carlos
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bus_w16(CONTROL_REG, 0x0);*/
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return OK;
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}
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u_int32_t testFpga(void) {
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printf("Testing FPGA:\n");
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volatile u_int32_t val,addr,val2;
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int result=OK,i;
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//fixed pattern
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val=bus_r(FIX_PATT_REG);
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if (val==FIXED_PATT_VAL) {
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printf("fixed pattern ok!! %08x\n",val);
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} else {
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printf("fixed pattern wrong!! %08x\n",val);
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result=FAIL;
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}
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printf("\nTesting FPGA...\n");
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//dummy register
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addr = DUMMY_REG;
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for(i=0;i<1000000;i++)
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{
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val=0x5A5A5A5A-i;
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bus_w(addr, val);
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val=bus_r(addr);
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if (val!=0x5A5A5A5A-i) {
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printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of %x \n",i,val,0x5A5A5A5A-i);
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result=FAIL;
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}
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val=(i+(i<<10)+(i<<20));
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bus_w(addr, val);
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val2=bus_r(addr);
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if (val2!=val) {
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printf("ATTEMPT:%d:\tFPGA dummy register wrong!! read %x instead of %x.\n",i,val2,val);
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result=FAIL;
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}
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val=0x0F0F0F0F;
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bus_w(addr, val);
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val=bus_r(addr);
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if (val!=0x0F0F0F0F) {
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printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of 0x0F0F0F0F \n",i,val);
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result=FAIL;
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}
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val=0xF0F0F0F0;
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bus_w(addr, val);
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val=bus_r(addr);
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if (val!=0xF0F0F0F0) {
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printf("ATTEMPT:%d:\tFPGA dummy register wrong!! %x instead of 0xF0F0F0F0 \n\n",i,val);
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result=FAIL;
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}
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}
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if(result==OK)
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{
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printf("----------------------------------------------------------------------------------------------");
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printf("\nATTEMPT 1000000: FPGA DUMMY REGISTER OK!!!\n");
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printf("----------------------------------------------------------------------------------------------");
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//fixed pattern
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int ret = OK;
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volatile u_int32_t val = bus_r(FIX_PATT_REG);
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if (val == FIX_PATT_VAL) {
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printf("Fixed pattern: successful match 0x%08x\n",val);
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} else {
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cprintf(RED,"Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n", val, FIX_PATT_VAL);
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ret = FAIL;
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}
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printf("\n");
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return result;
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return ret;
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}
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u_int32_t testRAM(void) {
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int result=OK;
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printf("TestRAM not implemented\n");
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printf("RAM Test not implemented!\n");
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return result;
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}
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int testBus() {
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printf("\nTesting Bus...\n");
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int ret = OK;
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u_int32_t addr = SET_DELAY_LSB_REG;
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int times = 1000 * 1000;
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int i = 0;
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for (i = 0; i < times; ++i) {
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bus_w(addr, i * 100);
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if (i * 100 != bus_r(SET_DELAY_LSB_REG)) {
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cprintf(RED,"ERROR: Mismatch! Wrote 0x%x, read 0x%x\n", i * 100, bus_r(SET_DELAY_LSB_REG));
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ret = FAIL;
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}
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}
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if (ret == OK)
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printf("Successfully tested bus %d times\n", times);
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printf("\n");
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return ret;
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}
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int getNModBoard() {
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return 1;
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@ -1139,15 +1141,6 @@ int getNMod() {
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}
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// fifo test
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int testFifos(void) {
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printf("Fifo test not implemented!\n");
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bus_w16(CONTROL_REG, START_FIFOTEST_BIT);
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bus_w16(CONTROL_REG, 0x0);
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return OK;
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}
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// program dacq settings
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@ -1660,21 +1653,8 @@ int configureInterface(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int
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#endif
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//bus_w(CONTROL_REG,GB10_RESET_BIT);
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//usleep(50 * 1000);
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bus_w(CONTROL_REG,0);
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//usleep(500* 1000);
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//bus_w(CONFIG_REG,conf | GB10_NOT_CPU_BIT);
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printf("System status register is %08x\n",bus_r(SYSTEM_STATUS_REG));
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/*
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bus_w(CONTROL_REG,GB10_RESET_BIT);
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bus_w(CONTROL_REG,0);
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usleep(500 * 1000);
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bus_w(CONFIG_REG,conf | GB10_NOT_CPU_BIT);
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printf("System status register is %08x\n",bus_r(SYSTEM_STATUS_REG));
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*/
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/*bus_w(CONTROL_REG,0); Carlos modification
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printf("System status register is %08x\n",bus_r(SYSTEM_STATUS_REG));*/
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printf("Reset mem machine fifos\n");
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bus_w(MEM_MACHINE_FIFOS_REG,0x4000);
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@ -1733,31 +1713,19 @@ int getAdcConfigured(){
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}
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u_int32_t runBusy(void) {
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u_int32_t s = bus_r(STATUS_REG) & 1;
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u_int32_t s = ((runState() & RUN_BUSY_MSK) >> RUN_BUSY_OFST);
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#ifdef VERBOSE
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printf("status %04x\n",s);
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#endif
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return s;
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}
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u_int32_t dataPresent(void) {
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return bus_r(LOOK_AT_ME_REG);
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}
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u_int32_t runState(void) {
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int s=bus_r(STATUS_REG);
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#ifdef SHAREDMEMORY
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if (s&RUN_BUSY_BIT)
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write_status_sm("Running");
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else
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write_status_sm("Stopped");
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#endif
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#ifdef VERBOSE
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printf("status %04x\n",s);
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#endif
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/* if (s==0x62001)
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exit(-1);*/
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return s;
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}
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@ -1771,10 +1739,6 @@ int startStateMachine(){
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//#endif
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// cleanFifo();
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// fifoReset();
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#ifdef SHAREDMEMORY
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write_stop_sm(0);
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write_status_sm("Started");
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#endif
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//start state machine
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bus_w16(CONTROL_REG, FIFO_RESET_BIT);
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bus_w16(CONTROL_REG, 0x0);
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@ -1792,10 +1756,6 @@ int stopStateMachine(){
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//#ifdef VERBOSE
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cprintf(BG_RED,"*******Stopping State Machine*******\n");
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//#endif
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#ifdef SHAREDMEMORY
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write_stop_sm(1);
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write_status_sm("Stopped");
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#endif
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// for(i=0;i<100;i++){
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//stop state machine
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bus_w16(CONTROL_REG, STOP_ACQ_BIT);
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@ -1808,11 +1768,9 @@ int stopStateMachine(){
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int startReadOut(){
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u_int32_t status;
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#ifdef VERBOSE
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printf("Starting State Machine Readout\n");
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#endif
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status=bus_r(STATUS_REG)&RUN_BUSY_BIT;
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#ifdef DEBUG
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printf("State machine status is %08x\n",bus_r(STATUS_REG));
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#endif
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@ -1822,6 +1780,57 @@ int startReadOut(){
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return OK;
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}
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enum runStatus getStatus() {
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#ifdef VERBOSE
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printf("Getting status\n");
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#endif
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enum runStatus s;
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u_int32_t retval = runState();
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printf("\n\nSTATUS=%08x\n",retval);
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//running
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if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) {
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if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) {
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printf("-----------------------------------WAITING-----------------------------------\n");
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s=WAITING;
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}
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else{
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printf("-----------------------------------RUNNING-----------------------------------\n");
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s=RUNNING;
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}
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}
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//not running
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else {
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if ((retval & STOPPED_MSK) >> STOPPED_OFST) {
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printf("-----------------------------------STOPPED--------------------------\n");
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s=STOPPED;
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} else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) {
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printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
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s=TRANSMITTING;
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} else if (!retval) {
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printf("-----------------------------------IDLE--------------------------------------\n");
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s=IDLE;
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} else {
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printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
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s=ERROR;
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}
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/* Check with Carlos , I included IDLE and unknown status above
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//and readbusy=0,idle
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else if((!(retval&0xffff))||(retval==SOME_FIFO_FULL_BIT)){
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printf("-----------------------------------IDLE--------------------------------------\n");
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s=IDLE;
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} else {
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printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
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s=ERROR;
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ret=FAIL;
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}*/
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}
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return s;
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}
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// fifo routines
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@ -1942,38 +1951,6 @@ int getDynamicRange() {
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return dynamicRange;
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}
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int testBus() {
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u_int32_t j;
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u_int64_t i, n, nt;
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// char cmd[100];
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u_int32_t val=0x0;
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int ifail=OK;
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// printf("%s\n",cmd);
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// system(cmd);
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i=0;
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n=1000000;
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nt=n/100;
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printf("testing bus %d times\n",(int)n);
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while (i<n) {
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// val=bus_r(FIX_PATT_REG);
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bus_w(DUMMY_REG,val);
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bus_w(FIX_PATT_REG,0);
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j=bus_r(DUMMY_REG);
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//if (i%10000==1)
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if (j!=val){
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printf("%d : read wrong value %08x instead of %08x\n",(int)i,j, val);
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ifail++;
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//return FAIL;
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}// else
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// printf("%d : value OK 0x%08x\n",i,j);
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if ((i%nt)==0)
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printf("%lld cycles OK\n",i);
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val+=0xbbbbb;
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i++;
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}
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return ifail;
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}
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int setStoreInRAM(int b) {
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@ -28,6 +28,9 @@ void FPGAdontTouchFlash();
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void FPGATouchFlash();
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int powerChip (int on);
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void initializeDetector();
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int checkType();
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void printVersions();
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u_int16_t bus_r16(u_int32_t offset);
|
||||
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
|
||||
@ -90,8 +93,8 @@ int getAdcConfigured();
|
||||
|
||||
|
||||
u_int64_t getDetectorNumber();
|
||||
u_int32_t getFirmwareVersion();
|
||||
u_int32_t getFirmwareSVNVersion();
|
||||
u_int64_t getFirmwareVersion();
|
||||
int64_t getId(enum idMode arg);
|
||||
|
||||
int testFifos(void);
|
||||
u_int32_t testFpga(void);
|
||||
@ -136,12 +139,12 @@ int64_t getFramesFromStart();
|
||||
|
||||
u_int32_t runBusy(void);
|
||||
u_int32_t runState(void);
|
||||
u_int32_t dataPresent(void);
|
||||
|
||||
|
||||
int startStateMachine();
|
||||
int stopStateMachine();
|
||||
int startReadOut();
|
||||
enum runStatus getStatus();
|
||||
u_int32_t fifoReset(void);
|
||||
u_int32_t fifoReadCounter(int fifonum);
|
||||
u_int32_t fifoReadStatus();
|
||||
|
@ -9,6 +9,70 @@
|
||||
#define CSP0 0x20200000
|
||||
#define MEM_SIZE 0x100000
|
||||
|
||||
/* FPGA Version register */
|
||||
|
||||
#define FPGA_VERSION_REG (0x00 << 11)
|
||||
|
||||
#define BOARD_REVISION_OFST (0)
|
||||
#define BOARD_REVISION_MSK (0x00FFFFFF << BOARD_REVISION_OFST)
|
||||
#define DETECTOR_TYPE_OFST (24)
|
||||
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
|
||||
|
||||
|
||||
|
||||
/* Fix pattern register */
|
||||
#define FIX_PATT_REG (0x01 << 11)
|
||||
|
||||
#define FIX_PATT_VAL 0xACDC2014
|
||||
|
||||
|
||||
/* Status register */
|
||||
#define STATUS_REG (0x02 << 11)
|
||||
|
||||
#define RUN_BUSY_OFST (0)
|
||||
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_BIT_OFST)
|
||||
#define WAITING_FOR_TRIGGER_OFST (3)
|
||||
#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
|
||||
#define DELAYBEFORE_OFST (4)
|
||||
#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST)
|
||||
#define DELAYAFTER_OFST (5)
|
||||
#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST)
|
||||
#define STOPPED_OFST (15)
|
||||
#define STOPPED_MSK (0x00000001 << STOPPED_OFST)
|
||||
#define RUNMACHINE_BUSY_OFST (17)
|
||||
#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
|
||||
|
||||
|
||||
/* Look at me register */
|
||||
#define LOOK_AT_ME_REG (0x03 << 11) //Not used in firmware or software
|
||||
|
||||
/* System Status register */
|
||||
#define SYSTEM_STATUS_REG (0x04 << 11) //Not used in software
|
||||
|
||||
#define DDR3_CAL_DONE_OFST (0)
|
||||
#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST)
|
||||
#define DDR3_CAL_FAIL_OFST (1)
|
||||
#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST)
|
||||
#define DDR3_CAL_FAIL_OFST (1)
|
||||
#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST)
|
||||
|
||||
|
||||
|
||||
|
||||
/* Time from Start 64 bit register */
|
||||
#define TIME_FROM_START_LSB_REG (0x10 << 11)
|
||||
#define TIME_FROM_START_MSB_REG (0x11 << 11)
|
||||
//#define GET_ACTUAL_TIME_LSB_REG 16<<11
|
||||
//#define GET_ACTUAL_TIME_MSB_REG 17<<11
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//Constants
|
||||
#define HALFSPEED_DBIT_PIPELINE 0x7f7c
|
||||
@ -22,7 +86,7 @@
|
||||
|
||||
/* values defined for FPGA */
|
||||
#define MCSNUM 0x0
|
||||
#define FIXED_PATT_VAL 0xacdc1980
|
||||
|
||||
|
||||
|
||||
#define FPGA_INIT_PAT 0x60008
|
||||
@ -64,12 +128,11 @@
|
||||
//HV
|
||||
|
||||
|
||||
#define DUMMY_REG 0x44<<11
|
||||
#define FPGA_VERSION_REG 0<<11 //0x22<<11
|
||||
#define PCB_REV_REG 0<<11
|
||||
#define FIX_PATT_REG 1<<11 //0x23<<11
|
||||
|
||||
|
||||
|
||||
#define CONTROL_REG 79<<11//0x24<<11
|
||||
#define STATUS_REG 2<<11 //0x25<<11
|
||||
|
||||
#define CONFIG_REG 77<<11//0x26<<11
|
||||
#define EXT_SIGNAL_REG 78<<11// 0x4E<<11
|
||||
#define FPGA_SVN_REG 0x29<<11
|
||||
@ -78,8 +141,8 @@
|
||||
#define CHIP_OF_INTRST_REG 0x2A<<11
|
||||
|
||||
//FIFO
|
||||
#define LOOK_AT_ME_REG 3<<11 //0x28<<11
|
||||
#define SYSTEM_STATUS_REG 4<<11
|
||||
|
||||
|
||||
|
||||
#define FIFO_DATA_REG 6<<11
|
||||
#define FIFO_STATUS_REG 7<<11
|
||||
@ -99,8 +162,7 @@
|
||||
|
||||
|
||||
|
||||
#define GET_ACTUAL_TIME_LSB_REG 16<<11
|
||||
#define GET_ACTUAL_TIME_MSB_REG 17<<11
|
||||
|
||||
|
||||
#define GET_MEASUREMENT_TIME_LSB_REG 38<<11
|
||||
#define GET_MEASUREMENT_TIME_MSB_REG 38<<11
|
||||
@ -268,13 +330,7 @@
|
||||
#define SHIFTMOD 2
|
||||
#define SHIFTFIFO 9
|
||||
|
||||
/** for PCB_REV_REG */
|
||||
#define DETECTOR_TYPE_MASK 0xFF000000
|
||||
#define DETECTOR_TYPE_OFFSET 24
|
||||
#define BOARD_REVISION_MASK 0xFFFFFF
|
||||
#define MOENCH03_MODULE_ID 2
|
||||
#define JUNGFRAU_MODULE_ID 8
|
||||
#define JUNGFRAU_CTB_ID 3
|
||||
|
||||
|
||||
|
||||
|
||||
@ -295,28 +351,7 @@
|
||||
#define GB10_RESET_BIT 0x0800
|
||||
#define MEM_RESET_BIT 0x1000
|
||||
|
||||
/* for status register */
|
||||
#define RUN_BUSY_BIT 0x00000001
|
||||
#define READOUT_BUSY_BIT 0x00000002
|
||||
#define FIFOTEST_BUSY_BIT 0x00000004 //????
|
||||
#define WAITING_FOR_TRIGGER_BIT 0x00000008
|
||||
#define DELAYBEFORE_BIT 0x00000010
|
||||
#define DELAYAFTER_BIT 0x00000020
|
||||
#define EXPOSING_BIT 0x00000040
|
||||
#define COUNT_ENABLE_BIT 0x00000080
|
||||
#define READSTATE_0_BIT 0x00000100
|
||||
#define READSTATE_1_BIT 0x00000200
|
||||
#define READSTATE_2_BIT 0x00000400
|
||||
#define SOME_FIFO_FULL_BIT 0x00000800 // error!
|
||||
|
||||
#define RUNSTATE_0_BIT 0x00001000
|
||||
#define RUNSTATE_1_BIT 0x00002000
|
||||
#define RUNSTATE_2_BIT 0x00004000
|
||||
#define STOPPED_BIT 0x00008000 // stopped!
|
||||
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
|
||||
#define RUNMACHINE_BUSY_BIT 0x00020000
|
||||
#define READMACHINE_BUSY_BIT 0x00040000
|
||||
#define PLL_RECONFIG_BUSY 0x00100000
|
||||
|
||||
|
||||
|
||||
|
@ -538,15 +538,9 @@ int get_id(int file_des) {
|
||||
|
||||
switch (arg) {
|
||||
case DETECTOR_SERIAL_NUMBER:
|
||||
retval=getDetectorNumber();
|
||||
break;
|
||||
case DETECTOR_FIRMWARE_VERSION:
|
||||
retval=getFirmwareSVNVersion();
|
||||
retval=(retval <<32) | getFirmwareVersion();
|
||||
break;
|
||||
case DETECTOR_SOFTWARE_VERSION:
|
||||
retval= SVNREV;
|
||||
retval= (retval <<32) | SVNDATE;
|
||||
retval = getId(arg);
|
||||
break;
|
||||
default:
|
||||
printf("Required unknown id %d \n", arg);
|
||||
@ -1700,44 +1694,9 @@ int get_run_status(int file_des) {
|
||||
enum runStatus s;
|
||||
sprintf(mess,"getting run status\n");
|
||||
|
||||
#ifdef VERBOSE
|
||||
printf("Getting status\n");
|
||||
#endif
|
||||
|
||||
retval= runState();
|
||||
printf("\n\nSTATUS=%08x\n",retval);
|
||||
|
||||
if(!(retval&RUN_BUSY_BIT)){
|
||||
if((retval&STOPPED_BIT) ){ //
|
||||
printf("-----------------------------------STOPPED--------------------------\n");
|
||||
s=STOPPED;
|
||||
} else if((retval&READMACHINE_BUSY_BIT) ){
|
||||
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
|
||||
s=TRANSMITTING;
|
||||
}
|
||||
//and readbusy=0,idle
|
||||
else if((!(retval&0xffff))||(retval==SOME_FIFO_FULL_BIT)){
|
||||
printf("-----------------------------------IDLE--------------------------------------\n");
|
||||
s=IDLE;
|
||||
} else {
|
||||
printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval);
|
||||
s=ERROR;
|
||||
ret=FAIL;
|
||||
}
|
||||
}
|
||||
//if runbusy=1
|
||||
else {
|
||||
if (retval&WAITING_FOR_TRIGGER_BIT){
|
||||
printf("-----------------------------------WAITING-----------------------------------\n");
|
||||
s=WAITING;
|
||||
}
|
||||
else{
|
||||
printf("-----------------------------------RUNNING-----------------------------------\n");
|
||||
s=RUNNING;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
s = getStatus();
|
||||
if (s == ERROR)
|
||||
ret = FAIL;
|
||||
|
||||
if (ret!=OK) {
|
||||
printf("get status failed %04x\n",retval);
|
||||
|
Loading…
x
Reference in New Issue
Block a user