first try

This commit is contained in:
froejdh_e
2025-12-11 15:42:20 +01:00
parent 654c16b52b
commit 38bc600dc9
2 changed files with 44 additions and 0 deletions

View File

@@ -1814,6 +1814,37 @@ class Detector(CppDetectorApi):
[Eiger] Address is +0x100 for only left, +0x200 for only right.
"""
return self._register
def define_reg(self, name, addr):
addr = RegisterAddress(addr)
self.setRegisterDefinition(name, addr)
def define_bit(self, name, addr, bitnr):
addr = RegisterAddress(addr)
bitnr = BitAddress(addr, bitnr)
self.setBitDefinition(name, bitnr)
def setBit(self, bit_or_addr, number=None):
#Old usage passing two ints
if isinstance(bit_or_addr, int):
return super().setBit(bit_or_addr, number)
#New usage with str or BitAddress
if isinstance(bit_or_addr, str):
bit_or_addr = self.getBitDefinition(bit_or_addr)
return super().setBit(bit_or_addr)
@property
def slowadc(self):

View File

@@ -1,13 +1,26 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
from ._slsdet import RegisterValue, RegisterAddress
class Register:
def __init__(self, detector):
self._detector = detector
def __getitem__(self, key):
if isinstance(key, str):
key = self._detector.getRegisterDefinition(key)
return self._detector.readRegister(key)
def __setitem__(self, key, value):
if isinstance(key, str):
key = self._detector.getRegisterDefinition(key)
elif isinstance(key, int):
key = RegisterAddress(key)
if isinstance(value, int):
value = RegisterValue(value)
self._detector.writeRegister(key, value, False)
class Adc_register: