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dev/xilinx_fifo_fix transceiver (#1313)
* xilinx ctb: clean fifos in a stop command for transceivers, else always running * refactor
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@@ -440,14 +440,18 @@ void cleanFifos() {
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#ifdef VIRTUAL
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return;
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#endif
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uint32_t t_enable_mask = getTransceiverEnableMask();
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uint32_t tclean_msk =
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((t_enable_mask << X_FIFO_CLEAN_OFST) & X_FIFO_CLEAN_MSK);
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uint32_t t_before_reg = bus_r(X_FIFO_CLEAN_REG);
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LOG(logINFO, ("Clearing Acquisition Fifos\n"));
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bus_w(A_FIFO_CLEAN_REG, bus_r(A_FIFO_CLEAN_REG) | BIT32_MSK);
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bus_w(D_FIFO_CLEAN_REG, bus_r(D_FIFO_CLEAN_REG) | D_FIFO_CLEAN_MSK);
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bus_w(X_FIFO_CLEAN_REG, bus_r(X_FIFO_CLEAN_REG) | X_FIFO_CLEAN_MSK);
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bus_w(X_FIFO_CLEAN_REG, t_before_reg | tclean_msk);
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bus_w(A_FIFO_CLEAN_REG, 0);
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bus_w(D_FIFO_CLEAN_REG, bus_r(D_FIFO_CLEAN_REG) & ~D_FIFO_CLEAN_MSK);
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bus_w(X_FIFO_CLEAN_REG, bus_r(X_FIFO_CLEAN_REG) & ~X_FIFO_CLEAN_MSK);
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bus_w(X_FIFO_CLEAN_REG, t_before_reg);
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}
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void resetFlow() {
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@@ -1639,7 +1643,7 @@ int stopStateMachine() {
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#endif
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// stop state machine
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bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | STOP_F_MSK);
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cleanFifos();
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return OK;
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}
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@@ -7,6 +7,6 @@
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#define APIGOTTHARD2 "0.0.0 0x250909"
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#define APIMOENCH "0.0.0 0x250909"
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#define APIEIGER "0.0.0 0x250909"
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#define APIXILINXCTB "0.0.0 0x250924"
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#define APIXILINXCTB "0.0.0 0x250930"
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#define APIJUNGFRAU "0.0.0 0x250909"
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#define APIMYTHEN3 "0.0.0 0x250922"
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