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This commit is contained in:
Dhanya Maliakal 2016-10-25 08:18:02 +02:00
parent 94ff6cb092
commit 31d48411db
4 changed files with 241 additions and 156 deletions
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61
slsDetectorSoftware/jungfrauDetectorServer/firmware_funcs.c
View File

@ -103,6 +103,7 @@ u_int32_t clkDivider[2]={32,16};
#else #else
u_int32_t clkDivider[2]={40,20}; u_int32_t clkDivider[2]={40,20};
#endif #endif
static const int JUNGFRAU_CLOCK = 1;
int32_t clkPhase[2]={0,0}; int32_t clkPhase[2]={0,0};
u_int32_t adcDisableMask=0; u_int32_t adcDisableMask=0;
@ -288,7 +289,7 @@ int cleanFifo(){
int setDAQRegister() int setDAQRegister()
{ {
/* u_int32_t addr, reg, val; */ /* u_int32_t addr, reg, val; */
/* addr=DAQ_REG; */ /* addr=CONFGAIN_REG; */
/* //depended on adcval */ /* //depended on adcval */
/* int packetlength=0x7f; */ /* int packetlength=0x7f; */
@ -450,8 +451,10 @@ void configurePll(int i) {
if (i<2) { if (i<2) {
if(myDetectorType == JUNGFRAU)
tot= PLL_VCO_FREQ_MHZ/clkDivider[i]; tot= PLL_VCO_FREQ_MHZ/clkDivider[JUNGFRAU_CLOCK];
else
tot= PLL_VCO_FREQ_MHZ/clkDivider[i];
l=tot/2; l=tot/2;
h=l; h=l;
if (tot>2*l) { if (tot>2*l) {
@ -553,6 +556,41 @@ void configurePll(int i) {
u_int32_t setClockDivider(int d, int ic) { u_int32_t setClockDivider(int d, int ic) {
if(myDetectorType == JUNGFRAU){
enum clkspeed{FULL,HALF,QUARTER};
switch((clkspeed)d){
//stop state machine if running
if(runBusy())
stopStateMachine();
case FULL:
printf("Setting Half Speed (40 MHz)\n");
/**to be done*/
break;
case HALF:
printf("Setting Half Speed (20 MHz)\n");
sls_detector_put reg 0x59 0x7f7c
sls_detector_put reg 0x42 0x20
sls_detector_put status stop
sls_detector_put reg 0x5d 0x00000f00
sls_detector_put adcphase 65
sls_detector_put status start
break;
case QUARTER:
printf("Setting Half Speed (10 MHz)\n");
sls_detector_put reg 0x59 0x8981
sls_detector_put reg 0x42 0x10
sls_detector_put reg 0x5d 0xf0000f00
sls_detector_put adcphase 25
sls_detector_put status start
break;
}
}
//u_int32_t l=0x0c; //u_int32_t l=0x0c;
//u_int32_t h=0x0d; //u_int32_t h=0x0d;
@ -560,7 +598,10 @@ u_int32_t setClockDivider(int d, int ic) {
u_int32_t tot= PLL_VCO_FREQ_MHZ/d; u_int32_t tot= PLL_VCO_FREQ_MHZ/d;
// int ic=0 is run clk; ic=1 is adc clk // int ic=0 is run clk; ic=1 is adc clk
printf("set clk divider %d to %d\n", ic, d); if(myDetectorType == JUNGFRAU)
printf("set clk divider to %d\n", ic, d);
else{
printf("set clk divider %d to %d\n", ic, d);
if (ic>1) if (ic>1)
return -1; return -1;
@ -575,7 +616,7 @@ u_int32_t setClockDivider(int d, int ic) {
if (tot<1) if (tot<1)
return -1; return -1;
}
clkDivider[ic]=d; clkDivider[ic]=d;
@ -586,6 +627,10 @@ u_int32_t setClockDivider(int d, int ic) {
return clkDivider[ic]; return clkDivider[ic];
} }
int adcPhase(int st){
return phaseStep(st); //name is wrong, but it resets pll and set the phase as st
}
int phaseStep(int st){ int phaseStep(int st){
@ -663,6 +708,12 @@ u_int32_t adcPipeline(int d) {
} }
u_int32_t dbitPipeline(int d){
if (d>=0)
bus_w(DAQ_REG, d);
return bus_r(DAQ_REG)&0xff;
}
u_int32_t setSetLength(int d) { u_int32_t setSetLength(int d) {
return 0; return 0;
} }

2
slsDetectorSoftware/jungfrauDetectorServer/firmware_funcs.h
View File

@ -30,6 +30,7 @@ u_int32_t bus_r(u_int32_t offset);
int setPhaseShiftOnce(); int setPhaseShiftOnce();
int phaseStep(int st); int phaseStep(int st);
int adcPhase(int st);
int getPhase(); int getPhase();
int cleanFifo(); int cleanFifo();
int setDAQRegister(); int setDAQRegister();
@ -53,6 +54,7 @@ u_int32_t setTotDutyCycle(int d);
u_int32_t getTotDutyCycle(); u_int32_t getTotDutyCycle();
u_int32_t setOversampling(int d); u_int32_t setOversampling(int d);
u_int32_t adcPipeline(int d); u_int32_t adcPipeline(int d);
u_int32_t dbitPipeline(int d);
u_int32_t setExtSignal(int d, enum externalSignalFlag mode); u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
int getExtSignal(int d); int getExtSignal(int d);

30
slsDetectorSoftware/jungfrauDetectorServer/registers_m.h
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@ -21,23 +21,23 @@
//#ifdef JUNGFRAU_DHANYA //#ifdef JUNGFRAU_DHANYA
#define POWER_ON_REG 0x5e<<11 #define POWER_ON_REG 0x5e<<11
#define ADCREG1 8 //same as PLL_BANDWIDTH_REG #define ADCREG1 0x8 //same as PLL_BANDWIDTH_REG
#define ADCREG2 20 //0x14 #define ADCREG2 0x14
#define ADCREG3 4 //same as PLL_M_COUNTER_REG #define ADCREG3 0x4 //same as PLL_M_COUNTER_REG
#define ADCREG4 5 //same as PLL_C_COUNTER_REG #define ADCREG4 0x5 //same as PLL_C_COUNTER_REG
#define ADCREG_VREFS 24 //0x18 #define ADCREG_VREFS 0x18
#define DBIT_PIPELINE_REG 89<<11 //0x59 same PATTERN_N_LOOP2_REG #define DBIT_PIPELINE_REG 0x59<<11 //same PATTERN_N_LOOP2_REG
#define MEM_MACHINE_FIFOS_REG 79<<11 //0x4f same as CONTROL_REG #define MEM_MACHINE_FIFOS_REG 0x4f<<11 //same as CONTROL_REG
#define CONFGAIN_REG 93<<11 //0x5d same as DAQ_REG #define CONFGAIN_REG 0x5d<<11 //same as DAQ_REG
#define ADC_PIPELINE_REG 66<<11 //0x42 same as ADC_OFFSET_REG #define ADC_PIPELINE_REG 0x42<<11 //same as ADC_OFFSET_REG
//#endif //#endif
#define ADC_OFFSET_REG 66<<11 //same as ADC_PIPELINE_REG //#define ADC_OFFSET_REG 66<<11 //same as CONFGAIN_REG
#define ADC_INVERSION_REG 67<<11 #define ADC_INVERSION_REG 0x43<<11
#define DAC_REG 64<<11//0x17<<11// control the dacs #define DAC_REG 64<<11//0x17<<11// control the dacs
//ADC //ADC
#define ADC_WRITE_REG 65<<11//0x18<<11 #define ADC_WRITE_REG 65<<11//0x18<<11
//#define ADC_SYNC_REG 66<<11//0x19<<11 //#define ADC_SYNC_REG 66<<11//0x19<<11
//#define HV_REG 67<<11//0x20<<11 //#define HV_REG 67<<11//0x20<<11
@ -55,7 +55,7 @@
//HV //HV
#define DUMMY_REG 68<<11//0x21<<11 #define DUMMY_REG 0x44<<11
#define FPGA_VERSION_REG 0<<11 //0x22<<11 #define FPGA_VERSION_REG 0<<11 //0x22<<11
#define PCB_REV_REG 0<<11 #define PCB_REV_REG 0<<11
#define FIX_PATT_REG 1<<11 //0x23<<11 #define FIX_PATT_REG 1<<11 //0x23<<11
@ -182,7 +182,7 @@
#define DAQ_REG 93<<11 //#define DAQ_REG 0x5d<<11 //same as CONFGAIN_REG
#define ADC_LATCH_DISABLE_REG 94<<11 #define ADC_LATCH_DISABLE_REG 94<<11
#define HV_REG 95<<11 #define HV_REG 95<<11

308
slsDetectorSoftware/jungfrauDetectorServer/server_funcs.c
View File

@ -144,39 +144,33 @@ int init_detector(int b, int checkType) {
initDac(0); initDac(8); //initializes the two dacs initDac(0); initDac(8); //initializes the two dacs
if(myDetectorType==JUNGFRAU){ if(myDetectorType==JUNGFRAU){
/** for jungfrau reinitializing macro */ //reinitialize macro
N_CHAN=JUNGFRAU_NCHAN; N_CHAN=JUNGFRAU_NCHAN;
N_CHIP=JUNGFRAU_NCHIP; N_CHIP=JUNGFRAU_NCHIP;
N_DAC=JUNGFRAU_NDAC; N_DAC=JUNGFRAU_NDAC;
N_ADC=JUNGFRAU_NADC; N_ADC=JUNGFRAU_NADC;
N_CHANS=JUNGFRAU_NCHANS; N_CHANS=JUNGFRAU_NCHANS;
//set dacs //set dacs
enum dacNames{VB_COMP,VDD_PROT,VIN_COM,VREF_PRECH,VB_PIXBUF,VB_DS,VREF_DS,VREF_COMP};
int retval = -1; int retval = -1;
int dacvalues[14][2]={ int dacvalues[14][2]={
{0, 1250}, //vout_cm {VB_DS, 1000},
{10, 1053}, //vin_com {VB_COMP, 1220},
{1, 600}, //vb_sda {VB_PIXBUF, 750},
{11, 1000}, //vb_colbuf {VREF_DS, 480},
{2, 3000}, //vb_test_cur {VREF_COMP, 400},
{3, 830}, //vcascp_pixbuf {VREF_PRECH,1550},
{4, 1630}, //vcascn_pixbuf {VIN_COM, 1053},
{12, 750}, //vb_pixbuf {VDD_PROT, 3000},
{6, 480}, //vref_ds
{5, 1000}, //vb_ds
{7, 400}, //vref_comp
{13, 1220}, //vb_comp
{8, 1500}, //vref_prech
{9, 3000}, //vdd_prot
}; };
for(i=0;i<14;++i){ for(i=0;i<8;++i){
retval=setDac(dacvalues[i][0], dacvalues[i][1]); retval=setDac(dacvalues[i][0], dacvalues[i][1]);
if(retval!=dacvalues[i][1]) if(retval!=dacvalues[i][1])
printf("Error: Setting dac %d failed, wrote %d, read %d\n",dacvalues[i][0],dacvalues[i][1],retval); printf("Error: Setting dac %d failed, wrote %d, read %d\n",dacvalues[i][0],dacvalues[i][1],retval);
} }
//power on the chips //power of the chips
bus_w(POWER_ON_REG,0x1); bus_w(POWER_ON_REG,0x1);
//reset adc //reset adc
@ -187,7 +181,6 @@ int init_detector(int b, int checkType) {
//vrefs - configurable? //vrefs - configurable?
writeADC(ADCREG_VREFS,0x2); writeADC(ADCREG_VREFS,0x2);
//set ADCINVERSionreg (by trial and error) //set ADCINVERSionreg (by trial and error)
bus_w(ADC_INVERSION_REG,0x453b2a9c); bus_w(ADC_INVERSION_REG,0x453b2a9c);
@ -195,8 +188,11 @@ int init_detector(int b, int checkType) {
bus_w(ADC_PIPELINE_REG,0x20); //same as ADC_OFFSET_REG bus_w(ADC_PIPELINE_REG,0x20); //same as ADC_OFFSET_REG
//set dbit_pipeline //set dbit_pipeline
bus_w(DBIT_PIPELINE_REG,0x100e); bus_w(DBIT_PIPELINE_REG,0x7f7c);
usleep(1000000);//1s
//set adc_clock_phase in unit of 1/(52) clock period (by trial and error)
adcPhase(65);
//reset mem machine fifos fifos //reset mem machine fifos fifos
bus_w(MEM_MACHINE_FIFOS_REG,0x4000); bus_w(MEM_MACHINE_FIFOS_REG,0x4000);
@ -208,16 +204,17 @@ int init_detector(int b, int checkType) {
//set default setting //set default setting
setSettings(DYNAMICGAIN,-1); setSettings(DYNAMICGAIN,-1);
/*setting the 4bits to 0x0 (MSB)*/
} }
//Initialization of acquistion parameters //Initialization of acquistion parameters
setFrames(-1); setFrames(1*1000*1000);
setTrains(-1); setTrains(-1);
setExposureTime(-1); setExposureTime(10*1000);
setPeriod(-1); setPeriod(2*1000*1000);
setDelay(-1); setDelay(0);
setGates(-1); setGates(0);
setTiming(GET_EXTERNAL_COMMUNICATION_MODE); setTiming(GET_EXTERNAL_COMMUNICATION_MODE);
setMaster(GET_MASTER); setMaster(GET_MASTER);
@ -1957,8 +1954,10 @@ int get_run_status(int file_des) {
printf("\n\nSTATUS=%08x\n",retval); printf("\n\nSTATUS=%08x\n",retval);
if(myDetectorType == JUNGFRAU){ if(myDetectorType == JUNGFRAU){
if(!(retval&RUN_BUSY_BIT)){ if(!(retval&RUN_BUSY_BIT)){
if((retval&STOPPED_BIT) ){ //
if((retval&READMACHINE_BUSY_BIT) ){ printf("-----------------------------------STOPPED--------------------------\n");
s=STOPPED;
} else if((retval&READMACHINE_BUSY_BIT) ){
printf("-----------------------------------READ MACHINE BUSY--------------------------\n"); printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
s=TRANSMITTING; s=TRANSMITTING;
} }
@ -2494,125 +2493,158 @@ int get_roi(int file_des) {
int set_speed(int file_des) { int set_speed(int file_des) {
enum speedVariable arg; enum speedVariable arg;
int val,n; int val,n;
int ret=OK; int ret=OK;
int retval; int retval=-1;
n=receiveDataOnly(file_des,&arg,sizeof(arg)); n=receiveDataOnly(file_des,&arg,sizeof(arg));
if (n < 0) { if (n < 0) {
sprintf(mess,"Error reading from socket\n"); sprintf(mess,"Error reading from socket\n");
ret=FAIL; ret=FAIL;
}
n=receiveDataOnly(file_des,&val,sizeof(val));
if (n < 0) {
sprintf(mess,"Error reading from socket\n");
ret=FAIL;
}
if (ret==OK) {
if (arg==PHASE_SHIFT || arg==ADC_PHASE) {
retval=phaseStep(val);
} else {
if (val!=-1) {
if (differentClients==1 && lockStatus==1 && val>=0) {
ret=FAIL;
sprintf(mess,"Detector locked by %s\n",lastClientIP);
} else {
switch (arg) {
case CLOCK_DIVIDER:
retval=setClockDivider(val,0);
break;
/* case PHASE_SHIFT: */
/* retval=phaseStep(val,0); */
/* break; */
case OVERSAMPLING:
retval=setOversampling(val);
break;
case ADC_CLOCK:
retval=setClockDivider(val,1);
break;
/* case ADC_PHASE: */
/* retval=phaseStep(val,1); */
/* break; */
case ADC_PIPELINE:
retval=adcPipeline(val);
break;
default:
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg);
} }
} n=receiveDataOnly(file_des,&val,sizeof(val));
} if (n < 0) {
sprintf(mess,"Error reading from socket\n");
ret=FAIL;
}
if (ret==OK) {
} if (val!=-1) {
if (differentClients==1 && lockStatus==1 && val>=0) {
ret=FAIL;
sprintf(mess,"Detector locked by %s\n",lastClientIP);
} else {
switch (arg) {
case CLOCK_DIVIDER:
if(myDetectorType == JUNGFRAU){
switch(val){
case 0:
ret=FAIL;
sprintf(mess,"Full speed not implemented yet. Available options: 1 for half speed and 2 for quarter speed");
break;
case 1:
case 2:
break;
default:
ret=FAIL;
sprintf(mess,"Unknown clock options %d. Available options: 1 for half speed and 2 for quarter speed",arg);
break;
}
}
setClockDivider(val,0);
break;
case PHASE_SHIFT:
if(myDetectorType == JUNGFRAU){
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d for this detector",arg);
break;
}
phaseStep(val);
break;
case OVERSAMPLING:
setOversampling(val);
break;
case ADC_CLOCK:
if(myDetectorType == JUNGFRAU){
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d for this detector",arg);
break;
}
setClockDivider(val,1);
break;
case ADC_PHASE:
if(myDetectorType == JUNGFRAU){
adcPhase(val);
break;
}
phaseStep(val);
break;
case ADC_PIPELINE:
if(myDetectorType == JUNGFRAU){
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d for this detector",arg);
break;
}
adcPipeline(val);
break;
switch (arg) { default:
case CLOCK_DIVIDER: ret=FAIL;
retval=getClockDivider(0); sprintf(mess,"Unknown speed parameter %d",arg);
break; }
}
case PHASE_SHIFT: }
retval=getPhase(); }
// retval=phaseStep(-1);
//ret=FAIL;
//sprintf(mess,"Cannot read phase",arg);
break;
case OVERSAMPLING:
retval=setOversampling(-1);
break;
case ADC_CLOCK:
retval=getClockDivider(1);
break;
case ADC_PHASE:
retval=getPhase();
break;
case ADC_PIPELINE:
retval=adcPipeline(-1);
break;
default:
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg);
}
}
n = sendDataOnly(file_des,&ret,sizeof(ret)); if (ret==OK) {
if (ret==FAIL) { switch (arg) {
n = sendDataOnly(file_des,mess,sizeof(mess)); case CLOCK_DIVIDER:
} else { retval=getClockDivider(0);
n = sendDataOnly(file_des,&retval,sizeof(retval)); break;
}
return ret; case PHASE_SHIFT:
if(myDetectorType == JUNGFRAU){
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d for this detector",arg);
break;
}
retval=getPhase();
break;
case OVERSAMPLING:
retval=setOversampling(-1);
break;
case ADC_CLOCK:
if(myDetectorType == JUNGFRAU){
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d for this detector",arg);
break;
}
retval=getClockDivider(1);
break;
case ADC_PHASE:
retval=getPhase();
break;
case ADC_PIPELINE:
if(myDetectorType == JUNGFRAU){
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d for this detector",arg);
break;
}
retval=adcPipeline(-1);
break;
default:
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg);
}
}
n = sendDataOnly(file_des,&ret,sizeof(ret));
if (ret==FAIL) {
n = sendDataOnly(file_des,mess,sizeof(mess));
} else {
n = sendDataOnly(file_des,&retval,sizeof(retval));
}
return ret;
} }