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hardware version (#580)

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* hardware version for all dets except eiger
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
This commit is contained in:
Dhanya Thattil
2022-11-24 11:24:05 +01:00
committed by GitHub
parent cd270160d8
commit 2ff5291f48
34 changed files with 359 additions and 156 deletions
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BIN
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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23
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -116,7 +116,9 @@ void basictests() {
return;
}
#endif
uint16_t hversion = getHardwareVersionNumber();
char hversion[MAX_STR_LENGTH] = {0};
memset(hversion, 0, MAX_STR_LENGTH);
getHardwareVersion(hversion);
uint16_t hsnumber = getHardwareSerialNumber();
uint32_t ipadd = getDetectorIP();
uint64_t macadd = getDetectorMAC();
@ -130,7 +132,7 @@ void basictests() {
sw_fw_apiversion = getFirmwareAPIVersion();
LOG(logINFOBLUE,
("**************************************************\n"
"Hardware Version:\t\t 0x%x\n"
"Hardware Version:\t\t %s\n"
"Hardware Serial Nr:\t\t 0x%x\n"
"Detector IP Addr:\t\t 0x%x\n"
@ -341,9 +343,24 @@ uint64_t getFirmwareAPIVersion() {
return ((bus_r(API_VERSION_REG) & API_VERSION_MSK) >> API_VERSION_OFST);
}
void getHardwareVersion(char *version) {
strcpy(version, "unknown");
int hwversion = getHardwareVersionNumber();
const int hwNumberList[] = HARDWARE_VERSION_NUMBERS;
const char *hwNamesList[] = HARDWARE_VERSION_NAMES;
for (int i = 0; i != NUM_HARDWARE_VERSIONS; ++i) {
LOG(logDEBUG, ("0x%x %d 0x%x %s\n", hwversion, i, hwNumberList[i],
hwNamesList[i]));
if (hwNumberList[i] == hwversion) {
strcpy(version, hwNamesList[i]);
return;
}
}
}
uint16_t getHardwareVersionNumber() {
#ifdef VIRTUAL
return 0;
return 0x3f;
#endif
return ((bus_r(MOD_SERIAL_NUMBER_REG) & MOD_SERIAL_NUMBER_VRSN_MSK) >>
MOD_SERIAL_NUMBER_VRSN_OFST);

154
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
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@ -7,10 +7,90 @@
#define MIN_REQRD_VRSN_T_RD_API 0x181130
#define REQRD_FRMWR_VRSN 0x220825
#define NUM_HARDWARE_VERSIONS (1)
#define HARDWARE_VERSION_NUMBERS \
{ 0x3f }
#define HARDWARE_VERSION_NAMES \
{ "5.1" }
#define LINKED_SERVER_NAME "ctbDetectorServer"
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
/* Hardware Definitions */
#define NCHAN (36)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (64)
#define NCHIP (1)
#define NDAC (24)
#define NPWR (6)
#define NDAC_ONLY (NDAC - NPWR)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) // MHz
#define I2C_POWER_VIO_DEVICE_ID (0x40)
#define I2C_POWER_VA_DEVICE_ID (0x41)
#define I2C_POWER_VB_DEVICE_ID (0x42)
#define I2C_POWER_VC_DEVICE_ID (0x43)
#define I2C_POWER_VD_DEVICE_ID (0x44)
#define I2C_SHUNT_RESISTER_OHMS (0.005)
/** Default Parameters */
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK (200) // 40
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define VCHIP_MIN_MV (1673)
#define VCHIP_MAX_MV (2668) // min dac val
#define POWER_RGLTR_MIN (636)
#define POWER_RGLTR_MAX \
(2638) // min dac val (not vchip-max) because of dac conversions
#define VCHIP_POWER_INCRMNT (200)
#define VIO_MIN_MV (1200) // for fpga to function
/* Defines in the Firmware */
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
@ -88,77 +168,3 @@ enum DACINDEX {
};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
/* Hardware Definitions */
#define NCHAN (36)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (64)
#define NCHIP (1)
#define NDAC (24)
#define NPWR (6)
#define NDAC_ONLY (NDAC - NPWR)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) // MHz
#define I2C_POWER_VIO_DEVICE_ID (0x40)
#define I2C_POWER_VA_DEVICE_ID (0x41)
#define I2C_POWER_VB_DEVICE_ID (0x42)
#define I2C_POWER_VC_DEVICE_ID (0x43)
#define I2C_POWER_VD_DEVICE_ID (0x44)
#define I2C_SHUNT_RESISTER_OHMS (0.005)
/** Default Parameters */
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK (200) // 40
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define VCHIP_MIN_MV (1673)
#define VCHIP_MAX_MV (2668) // min dac val
#define POWER_RGLTR_MIN (636)
#define POWER_RGLTR_MAX \
(2638) // min dac val (not vchip-max) because of dac conversions
#define VCHIP_POWER_INCRMNT (200)
#define VIO_MIN_MV (1200) // for fpga to function
/* Defines in the Firmware */
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)