Release of 5.1.0 (#237)

* Setting pattern from memory (#218)

* ToString accepts c-style arrays

* fixed patwait time bug in validation

* Introduced pattern class

* compile for servers too

* Python binding for Pattern

* added scanParameters in Python

* slsReceiver: avoid potential memory leak around Implementation::generalData

* additional constructors for scanPrameters in python

* bugfix: avoid potentital memory leak in receiver if called outside constructor context

* added scanParameters in Python

* additional constructors for scanPrameters in python

* M3defaultpattern (#227)

* default pattern for m3 and moench including Python bindings

* M3settings (#228)

* some changes to compile on RH7 and in the server to load the default chip status register at startup

* Updated mythen3DeectorServer_developer executable with correct initialization at startup

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>

* Pattern.h as a public header files (#229)

* fixed buffer overflow but caused by using global instead of local enum

* replacing out of range trimbits with edge values

* replacing dac values that are out of range after interpolation

* updated pybind11 to 2.6.2

* Mythen3 improved synchronization (#231)

Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master

* New server for JF to go with the new FW (#232)

* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218

* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.

* fix for m3 scan with single module

* m3 fw version

* m3 server

* bugfix for bottom when setting quad

* new strategy for finding zmq based on cppzmq



Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
This commit is contained in:
Erik Fröjdh
2021-03-22 14:43:11 +01:00
committed by GitHub
parent 64de9f3ad0
commit 2f2fe4dd47
168 changed files with 3614 additions and 9057 deletions

View File

@ -17,6 +17,7 @@ add_executable(mythen3DetectorServer_virtual
include_directories(
../slsDetectorServer/include
../../slsSupportLib/include
../../slsDetectorSoftware/include/sls/
)
target_include_directories(mythen3DetectorServer_virtual

View File

@ -2,10 +2,11 @@ current_dir = $(shell pwd)
main_inc = ../slsDetectorServer/include/
main_src = ../slsDetectorServer/src/
support_lib = ../../slsSupportLib/include/
det_lib = ../../slsDetectorSoftware/include/sls/
CROSS = nios2-buildroot-linux-gnu-
CC = $(CROSS)gcc
CFLAGS += -Wall -std=gnu99 -DMYTHEN3D -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) #-DDEBUG1 #-DVERBOSEI #-DVERBOSE
CFLAGS += -Wall -std=gnu99 -DMYTHEN3D -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(det_lib) -I$(current_dir) #-DDEBUG1 #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lrt -pthread
PROGS = mythen3DetectorServer
DESTDIR ?= bin

View File

@ -103,7 +103,12 @@
/* Look at me register, read only */
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL) // Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) // Not used in software
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL)
#define SYSTEM_STATUS_R_PLL_LCKD_OFST (1)
#define SYSTEM_STATUS_R_PLL_LCKD_MSK (0x00000001 << SYSTEM_STATUS_R_PLL_LCKD_OFST)
#define SYSTEM_STATUS_RDO_PLL_LCKD_OFST (2)
#define SYSTEM_STATUS_RDO_PLL_LCKD_MSK (0x00000001 << SYSTEM_STATUS_RDO_PLL_LCKD_OFST)
/* Config RW regiseter */
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
@ -483,6 +488,14 @@
/* ASIC Readout Control registers
* --------------------------------------------------*/
/** ASIC Readout Status register */
#define ASIC_RDO_STATUS_REG (0x00 * REG_OFFSET + BASE_ASIC_RDO)
#define ASIC_RDO_STATUS_BUSY_OFST (1)
#define ASIC_RDO_STATUS_BUSY_MSK (0x00000001 << ASIC_RDO_STATUS_BUSY_OFST)
/** ASIC Readout Res Storage Counter register */
#define ASIC_RDO_CONFIG_REG (0x01 * REG_OFFSET + BASE_ASIC_RDO)
#define ASICRDO_CNFG_RESSTRG_LNGTH_OFST (0)

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@ -19,6 +19,9 @@
#include <time.h>
#endif
/// NOT the right place to put it!
int setChipStatusRegister(int csr);
// Global variable from slsDetectorServer_funcs
extern int debugflag;
extern int updateFlag;
@ -40,6 +43,7 @@ pthread_t pthread_virtual_tid;
int64_t virtual_currentFrameNumber = 2;
#endif
enum detectorSettings thisSettings;
sls_detector_module *detectorModules = NULL;
int *detectorChans = NULL;
int *detectorDacs = NULL;
@ -50,8 +54,10 @@ uint32_t clkDivider[NUM_CLOCKS] = {};
int highvoltage = 0;
int detPos[2] = {};
int64_t exptimeReg[3] = {0, 0, 0};
int64_t gateDelayReg[3] = {0, 0, 0};
int64_t exptimeReg[NCOUNTERS] = {0, 0, 0};
int64_t gateDelayReg[NCOUNTERS] = {0, 0, 0};
int vthEnabledVals[NCOUNTERS] = {0, 0, 0};
int detID = 0;
int isInitCheckDone() { return initCheckDone; }
@ -264,13 +270,29 @@ u_int16_t getHardwareVersionNumber() {
MCB_SERIAL_NO_VRSN_OFST);
}
u_int32_t getDetectorNumber() {
#ifdef VIRTUAL
return 0;
void readDetectorNumber() {
#ifndef VIRTUAL
if (initError == FAIL) {
return;
}
FILE *fd = fopen(ID_FILE, "r");
if (fd == NULL) {
sprintf(initErrorMessage, "No %s file found.\n", ID_FILE);
LOG(logERROR, ("%s\n\n", initErrorMessage));
initError = FAIL;
return;
}
char output[255];
fgets(output, sizeof(output), fd);
sscanf(output, "%u", &detID);
if (isControlServer) {
LOG(logINFOBLUE, ("Detector ID: %u\n", detID));
}
#endif
return bus_r(MCB_SERIAL_NO_REG);
}
u_int32_t getDetectorNumber() { return detID; }
u_int64_t getDetectorMAC() {
#ifdef VIRTUAL
return 0;
@ -365,17 +387,19 @@ void allocateDetectorStructureMemory() {
(detectorModules)->reg = UNINITIALIZED;
(detectorModules)->iodelay = 0;
(detectorModules)->tau = 0;
(detectorModules)->eV = 0;
// thisSettings = UNINITIALIZED;
(detectorModules)->eV[0] = 0;
(detectorModules)->eV[1] = 0;
(detectorModules)->eV[2] = 0;
thisSettings = UNINITIALIZED;
// initialize dacs
for (int idac = 0; idac < (detectorModules)->ndac; ++idac) {
detectorDacs[idac] = 0;
}
// if trimval requested, should return -1 to acknowledge unknown
// trimbits start at 0 //TODO: restart server will not have 0 always
for (int ichan = 0; ichan < (detectorModules->nchan); ichan++) {
*((detectorModules->chanregs) + ichan) = -1;
*((detectorModules->chanregs) + ichan) = 0;
}
}
@ -401,10 +425,11 @@ void setupDetector() {
#endif
// pll defines
ALTERA_PLL_C10_SetDefines(REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL,
PLL_RESET_REG, PLL_RESET_REG,
PLL_RESET_READOUT_MSK, PLL_RESET_SYSTEM_MSK,
READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_SetDefines(
REG_OFFSET, BASE_READOUT_PLL, BASE_SYSTEM_PLL, PLL_RESET_REG,
PLL_RESET_READOUT_MSK, PLL_RESET_SYSTEM_MSK, SYSTEM_STATUS_REG,
SYSTEM_STATUS_RDO_PLL_LCKD_MSK, SYSTEM_STATUS_R_PLL_LCKD_MSK,
READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(READOUT_PLL);
ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL);
// hv
@ -438,7 +463,7 @@ void setupDetector() {
setTiming(DEFAULT_TIMING_MODE);
setNumIntGates(DEFAULT_INTERNAL_GATES);
setNumGates(DEFAULT_EXTERNAL_GATES);
for (int i = 0; i != 3; ++i) {
for (int i = 0; i != NCOUNTERS; ++i) {
setExpTime(i, DEFAULT_GATE_WIDTH);
setGateDelay(i, DEFAULT_GATE_DELAY);
}
@ -448,6 +473,11 @@ void setupDetector() {
#ifdef VIRTUAL
enableTenGigabitEthernet(0);
#endif
readDetectorNumber();
if (initError == FAIL) {
return;
}
setSettings(DEFAULT_SETTINGS);
// check module type attached if not in debug mode
{
@ -482,7 +512,12 @@ void setupDetector() {
}
powerChip(1);
loadDefaultPattern(DEFAULT_PATTERN_FILE);
if (initError != FAIL) {
initError = setChipStatusRegister(CSR_default);
//loadDefaultPattern(DEFAULT_PATTERN_FILE, initErrorMessage);
//startStateMachine(); //this was missing in previous code! runs the default pattern
}
setAllTrimbits(DEFAULT_TRIMBIT_VALUE);
}
int setDefaultDacs() {
@ -690,7 +725,7 @@ int getNumGates() { return bus_r(ASIC_EXP_EXT_GATE_NUMBER_REG); }
void updateGatePeriod() {
uint64_t max = 0;
uint32_t countermask = getCounterMask();
for (int i = 0; i != 3; ++i) {
for (int i = 0; i != NCOUNTERS; ++i) {
// only if counter enabled
if (countermask & (1 << i)) {
uint64_t sum = getExpTime(i) + getGateDelay(i);
@ -877,6 +912,7 @@ void setCounterMask(uint32_t arg) {
if (arg == 0 || arg > MAX_COUNTER_MSK) {
return;
}
uint32_t oldmask = getCounterMask();
LOG(logINFO, ("Setting counter mask to 0x%x\n", arg));
uint32_t addr = CONFIG_REG;
bus_w(addr, bus_r(addr) & ~CONFIG_COUNTERS_ENA_MSK);
@ -886,12 +922,21 @@ void setCounterMask(uint32_t arg) {
updatePacketizing();
LOG(logINFO, ("\tUpdating Exptime and Gate Delay\n"));
for (int i = 0; i < 3; ++i) {
for (int i = 0; i < NCOUNTERS; ++i) {
uint64_t ns = exptimeReg[i] / (1E-9 * getFrequency(SYSTEM_C0));
setExpTime(i, ns);
ns = gateDelayReg[i] / (1E-9 * getFrequency(SYSTEM_C0));
setGateDelay(i, ns);
}
LOG(logINFO, ("\tUpdating Vth dacs\n"));
for (int i = 0; i < NCOUNTERS; ++i) {
// if change in enable
if ((arg & (1 << i)) ^ (oldmask & (1 << i))) {
// will disable if counter disabled
setDAC(VTH1, vthEnabledVals[i], 0);
}
}
}
uint32_t getCounterMask() {
@ -1011,24 +1056,28 @@ int setModule(sls_detector_module myMod, char *mess) {
LOG(logINFO, ("Setting module\n"));
/* future implementation
// settings (not yet implemented)
setSettings((enum detectorSettings)myMod.reg);
// settings
if (myMod.reg >= 0) {
setSettings((enum detectorSettings)myMod.reg);
if (getSettings() != (enum detectorSettings)myMod.reg) {
sprintf(
mess,
"Could not set module. Could not set settings to %d, read %d\n",
myMod.reg, (int)getSettings());
LOG(logERROR, (mess));
return FAIL;
}
detectorModules->reg = myMod.reg;
}
// threshold
if (myMod.eV >= 0)
setThresholdEnergy(myMod.eV);
// custom trimbit file
else {
// (loading a random trim file) (dont return fail)
setSettings(UNDEFINED);
LOG(logERROR,
("Settings has been changed to undefined (random trim
file)\n"));
// changed for setsettings (direct),
// custom trimbit file (setmodule with myMod.reg as -1),
// change of dac (direct)
for (int i = 0; i < NCOUNTERS; ++i) {
setThresholdEnergy(i, -1);
}
}
*/
// dacs
for (int i = 0; i < NDAC; ++i) {
@ -1036,16 +1085,42 @@ int setModule(sls_detector_module myMod, char *mess) {
if (myMod.dacs[i] != -1) {
setDAC((enum DACINDEX)i, myMod.dacs[i], 0);
if (myMod.dacs[i] != detectorDacs[i]) {
sprintf(mess, "Could not set module. Could not set dac %d\n",
i);
// dont complain if that counter was disabled
if ((i == M_VTH1 || i == M_VTH2 || i == M_VTH3) &&
(detectorDacs[i] == DEFAULT_COUNTER_DISABLED_VTH_VAL)) {
continue;
}
sprintf(mess,
"Could not set module. Could not set dac %d, wrote %d, "
"read %d\n",
i, myMod.dacs[i], detectorDacs[i]);
LOG(logERROR, (mess));
// setSettings(UNDEFINED);
// LOG(logERROR, ("Settings has been changed to undefined\n"));
return FAIL;
}
}
}
// if settings given and cannot be validated (after setting dacs), return
// error
if (myMod.reg >= 0) {
if (getSettings() != (enum detectorSettings)myMod.reg) {
sprintf(
mess,
"Could not set module. The dacs in file do not correspond to "
"settings %d\n",
myMod.reg);
LOG(logERROR, (mess));
return FAIL;
}
}
// threshold
for (int i = 0; i < NCOUNTERS; ++i) {
if (myMod.eV[i] >= 0) {
setThresholdEnergy(i, myMod.eV[i]);
}
}
// trimbits
if (myMod.nchan == 0) {
LOG(logINFO, ("Setting module without trimbits\n"));
@ -1054,9 +1129,6 @@ int setModule(sls_detector_module myMod, char *mess) {
if (setTrimbits(myMod.chanregs) == FAIL) {
sprintf(mess, "Could not set module. Could not set trimbits\n");
LOG(logERROR, (mess));
// setSettings(UNDEFINED);
// LOG(logERROR, ("Settings has been changed to undefined (random "
// "trim file)\n"));
return FAIL;
}
}
@ -1236,6 +1308,7 @@ int setTrimbits(int *trimbits) {
}
int setAllTrimbits(int val) {
LOG(logINFO, ("Setting all trimbits to %d\n", val));
int *trimbits = malloc(sizeof(int) * ((detectorModules)->nchan));
for (int ichan = 0; ichan < ((detectorModules)->nchan); ++ichan) {
trimbits[ichan] = val;
@ -1245,11 +1318,14 @@ int setAllTrimbits(int val) {
free(trimbits);
return FAIL;
}
// setSettings(UNDEFINED);
// LOG(logERROR, ("Settings has been changed to undefined (random "
// "trim file)\n"));
LOG(logINFO, ("All trimbits have been set to %d\n", val));
free(trimbits);
// changed for setsettings (direct),
// custom trimbit file (setmodule with myMod.reg as -1),
// change of dac (direct)
for (int i = 0; i < NCOUNTERS; ++i) {
setThresholdEnergy(i, -1);
}
return OK;
}
@ -1267,6 +1343,73 @@ int getAllTrimbits() {
return value;
}
enum detectorSettings setSettings(enum detectorSettings sett) {
switch (sett) {
case STANDARD:
LOG(logINFOBLUE, ("Setting to standard settings\n"));
thisSettings = sett;
setDAC(M_VRPREAMP, DEFAULT_STANDARD_VRPREAMP, 0);
setDAC(M_VRSHAPER, DEFAULT_STANDARD_VRSHAPER, 0);
break;
case FAST:
LOG(logINFOBLUE, ("Setting to fast settings\n"));
thisSettings = sett;
setDAC(M_VRPREAMP, DEFAULT_FAST_VRPREAMP, 0);
setDAC(M_VRSHAPER, DEFAULT_FAST_VRSHAPER, 0);
break;
case HIGHGAIN:
LOG(logINFOBLUE, ("Setting to high gain settings\n"));
thisSettings = sett;
setDAC(M_VRPREAMP, DEFAULT_HIGHGAIN_VRPREAMP, 0);
setDAC(M_VRSHAPER, DEFAULT_HIGHGAIN_VRSHAPER, 0);
break;
default:
LOG(logERROR,
("Settings %d not defined for this detector\n", (int)sett));
return thisSettings;
}
LOG(logINFO, ("Settings: %d\n", thisSettings));
return thisSettings;
}
void validateSettings() {
if (detectorDacs[M_VRPREAMP] == DEFAULT_STANDARD_VRPREAMP &&
detectorDacs[M_VRSHAPER] == DEFAULT_STANDARD_VRSHAPER) {
if (thisSettings != STANDARD) {
thisSettings = STANDARD;
LOG(logINFOBLUE, ("Validated Settings changed to standard!\n"));
}
} else if (detectorDacs[M_VRPREAMP] == DEFAULT_FAST_VRPREAMP &&
detectorDacs[M_VRSHAPER] == DEFAULT_FAST_VRSHAPER) {
if (thisSettings != FAST) {
thisSettings = FAST;
LOG(logINFOBLUE, ("Validated Settings changed to fast!\n"));
}
} else if (detectorDacs[M_VRPREAMP] == DEFAULT_HIGHGAIN_VRPREAMP &&
detectorDacs[M_VRSHAPER] == DEFAULT_HIGHGAIN_VRSHAPER) {
if (thisSettings != HIGHGAIN) {
thisSettings = HIGHGAIN;
LOG(logINFOBLUE, ("Validated Settings changed to highgain!\n"));
}
} else {
thisSettings = UNDEFINED;
LOG(logWARNING,
("Settings set to undefined [vrpreamp: %d, vrshaper: %d]\n",
detectorDacs[M_VRPREAMP], detectorDacs[M_VRSHAPER]));
}
}
enum detectorSettings getSettings() { return thisSettings; }
int getThresholdEnergy(int counterIndex) {
return (detectorModules)->eV[counterIndex];
}
void setThresholdEnergy(int counterIndex, int eV) {
(detectorModules)->eV[counterIndex] = eV;
}
/* parameters - dac, hv */
void setDAC(enum DACINDEX ind, int val, int mV) {
if (val < 0) {
@ -1281,12 +1424,37 @@ void setDAC(enum DACINDEX ind, int val, int mV) {
setDAC(M_VTH3, val, mV);
return;
}
char *dac_names[] = {DAC_NAMES};
// remember vthx values and set 2800 if counter disabled
uint32_t counters = getCounterMask();
int vthdacs[] = {M_VTH1, M_VTH2, M_VTH3};
for (int i = 0; i < NCOUNTERS; ++i) {
if (vthdacs[i] == (int)ind) {
// remember enabled values for vthx
if (val != DEFAULT_COUNTER_DISABLED_VTH_VAL) {
int vthval = val;
if (mV) {
if (LTC2620_D_VoltageToDac(val, &vthval) == FAIL) {
return;
}
}
vthEnabledVals[i] = vthval;
LOG(logINFO, ("Remembering %s [%d]\n", dac_names[ind], vthval));
}
// set vthx to disable val, if counter disabled
if (!(counters & (1 << i))) {
LOG(logINFO, ("Disabling %s\n", dac_names[ind]));
val = DEFAULT_COUNTER_DISABLED_VTH_VAL;
mV = 0;
}
}
}
LOG(logDEBUG1, ("Setting dac[%d - %s]: %d %s \n", (int)ind, dac_names[ind],
val, (mV ? "mV" : "dac units")));
int dacval = val;
#ifdef VIRTUAL
LOG(logINFO, ("Setting dac[%d - %s]: %d %s \n", (int)ind, dac_names[ind],
val, (mV ? "mV" : "dac units")));
@ -1303,11 +1471,14 @@ void setDAC(enum DACINDEX ind, int val, int mV) {
detectorDacs[ind] = dacval;
}
#endif
if (ind == M_VRPREAMP || ind == M_VRSHAPER) {
validateSettings();
}
}
int getDAC(enum DACINDEX ind, int mV) {
if (ind == M_VTHRESHOLD) {
int ret[3] = {0};
int ret[NCOUNTERS] = {0};
ret[0] = getDAC(M_VTH1, mV);
ret[1] = getDAC(M_VTH2, mV);
ret[2] = getDAC(M_VTH3, mV);
@ -1351,8 +1522,16 @@ int setHighVoltage(int val) {
return highvoltage;
}
int isMaster(){
return !(bus_r(0x18) >> 31);
}
/* parameters - timing */
void setTiming(enum timingMode arg) {
if (!isMaster() && arg == AUTO_TIMING)
arg = TRIGGER_EXPOSURE;
uint32_t addr = CONFIG_REG;
switch (arg) {
case AUTO_TIMING:
@ -1719,8 +1898,8 @@ uint64_t readPatternWord(int addr) {
LOG(logDEBUG1, (" Reading Pattern Word (addr:0x%x)\n", addr));
uint32_t reg_lsb =
PATTERN_STEP0_LSB_REG +
addr * REG_OFFSET * 2; // the first word in RAM as base plus the offset
// of the word to write (addr)
addr * REG_OFFSET * 2; // the first word in RAM as base plus the
// offset of the word to write (addr)
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr * REG_OFFSET * 2;
// read value
@ -1750,8 +1929,8 @@ uint64_t writePatternWord(int addr, uint64_t word) {
// write word
uint32_t reg_lsb =
PATTERN_STEP0_LSB_REG +
addr * REG_OFFSET * 2; // the first word in RAM as base plus the offset
// of the word to write (addr)
addr * REG_OFFSET * 2; // the first word in RAM as base plus the
// offset of the word to write (addr)
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr * REG_OFFSET * 2;
set64BitReg(word, reg_lsb, reg_msb);
@ -2420,8 +2599,12 @@ int startReadOut() {
// start readout
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_READOUT_MSK);
LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
usleep(1);
while (bus_r(ASIC_RDO_STATUS_REG) & ASIC_RDO_STATUS_BUSY_MSK) {
usleep(1);
}
LOG(logINFOBLUE, ("Readout done\n"));
return OK;
}
@ -2472,9 +2655,9 @@ enum runStatus getRunStatus() {
uint32_t deadtimeReg = bus_r(DEADTIME_CONFIG_REG);
if ((deadtimeReg & DEADTIME_EARLY_EXP_FIN_ERR_MSK) >>
DEADTIME_EARLY_EXP_FIN_ERR_OFST) {
LOG(logERROR,
("Status: ERROR in Dead Time Reg (too short exptime) %08x\n",
deadtimeReg));
LOG(logERROR, ("Status: ERROR in Dead Time Reg (too short "
"exptime) %08x\n",
deadtimeReg));
s = ERROR;
}
// stopped or error
@ -2560,9 +2743,12 @@ int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod) {
destMod->iodelay = srcMod->iodelay;
if (srcMod->tau >= 0)
destMod->tau = srcMod->tau;
if (srcMod->eV >= 0)
destMod->eV = srcMod->eV;
*/
for (int i = 0; i < NCOUNTERS; ++i) {
if (srcMod->eV[i] >= 0)
destMod->eV[i] = srcMod->eV[i];
}
LOG(logDEBUG1, ("Copying register %x (%x)\n", destMod->reg, srcMod->reg));
if (destMod->nchan != 0) {
@ -2592,3 +2778,78 @@ int getTotalNumberOfChannels() {
int getNumberOfChips() { return NCHIP; }
int getNumberOfDACs() { return NDAC; }
int getNumberOfChannelsPerChip() { return NCHAN; }
int setChipStatusRegister(int csr) {
int iaddr=0;
int nbits=18;
int error=0;
//int start=0, stop=MAX_PATTERN_LENGTH, loop=0;
int patword=0;
patword=setBit(SIGNAL_STATLOAD,patword);
for (int i=0; i<2; i++)
writePatternWord(iaddr++, patword);
patword=setBit(SIGNAL_resStorage,patword);
patword=setBit(SIGNAL_resCounter,patword);
for (int i=0; i<8; i++)
writePatternWord(iaddr++, patword);
patword=clearBit(SIGNAL_resStorage,patword);
patword=clearBit(SIGNAL_resCounter,patword);
for (int i=0; i<8; i++)
writePatternWord(iaddr++, patword);
//#This version of the serializer pushes in the MSB first (compatible with the CSR bit numbering)
for (int ib=nbits-1; ib>=0; ib--) {
if (csr&(1<<ib))
patword=setBit(SIGNAL_serialIN,patword);
else
patword=clearBit(SIGNAL_serialIN,patword);
for (int i=0; i<4; i++)
writePatternWord(iaddr++, patword);
patword=setBit(SIGNAL_CHSclk,patword);
writePatternWord(iaddr++, patword);
patword=clearBit(SIGNAL_CHSclk,patword);
writePatternWord(iaddr++, patword);
}
patword=clearBit(SIGNAL_serialIN,patword);
for (int i=0; i<2; i++)
writePatternWord(iaddr++, patword);
patword=setBit(SIGNAL_STO,patword);
for (int i=0; i<5; i++)
writePatternWord(iaddr++, patword);
patword=clearBit(SIGNAL_STO,patword);
for (int i=0; i<5; i++)
writePatternWord(iaddr++, patword);
patword=clearBit(SIGNAL_STATLOAD,patword);
for (int i=0; i<5; i++)
writePatternWord(iaddr++, patword);
if (iaddr >= MAX_PATTERN_LENGTH) {
LOG(logERROR, ("Addr 0x%x is past max_address_length 0x%x!\n",
iaddr, MAX_PATTERN_LENGTH));
error = 1;
}
// set pattern wait address
for (int i = 0; i <= 2; i++)
setPatternWaitAddress(i, MAX_PATTERN_LENGTH - 1);
// pattern loop
for (int i = 0; i <= 2; i++) {
int stop = MAX_PATTERN_LENGTH - 1, nloop = 0;
setPatternLoop(i, &stop, &stop, &nloop);
}
// pattern limits
{
int start = 0, nloop = 0;
setPatternLoop(-1, &start, &iaddr, &nloop);
}
// send pattern to the chips
startPattern();
if (error != 0) {
return FAIL;
}
return OK;
}

View File

@ -1,8 +1,9 @@
#pragma once
#include "sls/sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN (0x200925)
#define REQRD_FRMWRE_VRSN (0x210201)
#define KERNEL_DATE_VRSN "Wed May 20 13:58:38 CEST 2020"
#define ID_FILE "detid_mythen3.txt"
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -25,24 +26,35 @@
#define MAX_EXT_SIGNALS (8)
/** Default Parameters */
#define DEFAULT_PATTERN_FILE ("DefaultPattern_mythen3.txt")
#define DEFAULT_INTERNAL_GATES (1)
#define DEFAULT_EXTERNAL_GATES (1)
#define DEFAULT_DYNAMIC_RANGE (32)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_GATE_WIDTH (100 * 1000 * 1000) // ns
#define DEFAULT_GATE_DELAY (0)
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // smp sample clk (x2), 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (10) //(100000000) // sync_clk, 100 MHz
#define DEFAULT_SYSTEM_C2 (10) //(100000000) // str_clk, 100 MHz
#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz
#define DEFAULT_PATTERN_FILE ("DefaultPattern_mythen3.txt")
#define DEFAULT_INTERNAL_GATES (1)
#define DEFAULT_EXTERNAL_GATES (1)
#define DEFAULT_DYNAMIC_RANGE (32)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_GATE_WIDTH (100 * 1000 * 1000) // ns
#define DEFAULT_GATE_DELAY (0)
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (STANDARD)
#define DEFAULT_TRIMBIT_VALUE (0)
#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
#define DEFAULT_STANDARD_VRPREAMP (1100)
#define DEFAULT_FAST_VRPREAMP (300)
#define DEFAULT_HIGHGAIN_VRPREAMP (1300)
#define DEFAULT_STANDARD_VRSHAPER (1280)
#define DEFAULT_FAST_VRSHAPER (1500)
#define DEFAULT_HIGHGAIN_VRSHAPER (1100)
#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
#define DEFAULT_READOUT_C1 (10) //(100000000) // smp sample clk (x2), 100 MHz
#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
#define DEFAULT_SYSTEM_C1 (10) //(100000000) // sync_clk, 100 MHz
#define DEFAULT_SYSTEM_C2 (10) //(100000000) // str_clk, 100 MHz
#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz
// (DEFAULT_SYSTEM_C3 only for timing receiver) should not be changed
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
@ -174,3 +186,19 @@ typedef struct udp_header_struct {
#define SIGNAL_resCounter (23)
#define SIGNAL_CHSclk (24)
#define SIGNAL_exposing (25)
//CHIP STARTUS REGISTER BITS
#define CSR_spypads 0
#define CSR_invpol 4
#define CSR_dpulse 5
#define CSR_interp 6
#define CSR_C10pre 7 //#default
#define CSR_pumprobe 8
#define CSR_apulse 9
#define CSR_C15sh 10
#define CSR_C30sh 11 //#default
#define CSR_C50sh 12
#define CSR_C225ACsh 13 // Connects 225fF SHAPER AC cap (1: 225 to shaper, 225 to GND. 0: 450 to shaper)
#define CSR_C15pre 14
#define CSR_default (1<<CSR_C10pre )|(1<< CSR_C30sh)