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Release of 5.1.0 (#237)

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* Setting pattern from memory (#218)

* ToString accepts c-style arrays

* fixed patwait time bug in validation

* Introduced pattern class

* compile for servers too

* Python binding for Pattern

* added scanParameters in Python

* slsReceiver: avoid potential memory leak around Implementation::generalData

* additional constructors for scanPrameters in python

* bugfix: avoid potentital memory leak in receiver if called outside constructor context

* added scanParameters in Python

* additional constructors for scanPrameters in python

* M3defaultpattern (#227)

* default pattern for m3 and moench including Python bindings

* M3settings (#228)

* some changes to compile on RH7 and in the server to load the default chip status register at startup

* Updated mythen3DeectorServer_developer executable with correct initialization at startup

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>

* Pattern.h as a public header files (#229)

* fixed buffer overflow but caused by using global instead of local enum

* replacing out of range trimbits with edge values

* replacing dac values that are out of range after interpolation

* updated pybind11 to 2.6.2

* Mythen3 improved synchronization (#231)

Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master

* New server for JF to go with the new FW (#232)

* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218

* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.

* fix for m3 scan with single module

* m3 fw version

* m3 server

* bugfix for bottom when setting quad

* new strategy for finding zmq based on cppzmq



Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
This commit is contained in:
Erik Fröjdh
2021-03-22 14:43:11 +01:00
committed by GitHub
parent 64de9f3ad0
commit 2f2fe4dd47
168 changed files with 3614 additions and 9057 deletions
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slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_5.1.0 Executable file
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slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServerv5.0.0
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7
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -1396,11 +1396,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
setPhase(ADC_CLK, adcPhase, 0);
LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", adcPhase));
// only implemented in the new boards now
if (!isHardwareVersion2()) {
setPhase(DBIT_CLK, dbitPhase, 0);
LOG(logINFO, ("\tSet DBIT Phase Reg to %d\n", dbitPhase));
}
setPhase(DBIT_CLK, dbitPhase, 0);
LOG(logINFO, ("\tSet DBIT Phase Reg to %d\n", dbitPhase));
return OK;
}

10
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -3,7 +3,7 @@
#include "sls/sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWRE_VRSN_BOARD2 0x200724 // 1.0 pcb
#define REQRD_FRMWRE_VRSN_BOARD2 0x210218 // 1.0 pcb
#define REQRD_FRMWRE_VRSN 0x200721 // 2.0 pcb
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -113,8 +113,8 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_OFST_FULL_SPEED_VAL (0x10) // 2.0 pcb
#define ADC_OFST_HALF_SPEED_VAL (0x08) // 2.0 pcb
#define ADC_OFST_QUARTER_SPEED_VAL (0x04) // 2.0 pcb
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x13) // 1.0 pcb (2 resistor network)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x0b) // 1.0 pcb (2 resistor network)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x10) // 1.0 pcb (2 resistor network)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x08) // 1.0 pcb (2 resistor network)
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
@ -140,8 +140,8 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_PHASE_FULL_SPEED (150) // 2.0 pcb
#define ADC_PHASE_HALF_SPEED (200) // 2.0 pcb
#define ADC_PHASE_QUARTER_SPEED (200) // 2.0 pcb
#define ADC_PHASE_HALF_SPEED_BOARD2 (75) // 1.0 pcb (2 resistor network)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (75) // 1.0 pcb (2 resistor network)
#define ADC_PHASE_HALF_SPEED_BOARD2 (110) // 1.0 pcb (2 resistor network)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220) // 1.0 pcb (2 resistor network)
#define DBIT_PHASE_FULL_SPEED (85) // 2.0 pcb
#define DBIT_PHASE_HALF_SPEED (150) // 2.0 pcb