mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-19 16:27:13 +02:00
gotthard compiles
This commit is contained in:
@ -1,6 +1,5 @@
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CROSS = bfin-uclinux-
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CC = $(CROSS)gcc
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CFLAGS += -Wall -DGOTTHARDD -DSTOP_SERVER # -DVERBOSE
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LDLIBS += -lm -lstdc++
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@ -158,10 +158,10 @@
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/* Fix Pattern register */
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#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
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#define FIXED_PATT_VAL (0xACDC1980)
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#define FIX_PATT_VAL (0xACDC1980)
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/** Config register */
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#define Config_REG (0x26 << MEM_MAP_SHIFT)
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#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
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#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
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#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
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@ -266,7 +266,7 @@
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#define DETECTOR_TYPE_MOENCH_VAL (2)
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/* 16 bit Fifo Data register */
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//#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
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#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
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/*
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#define MOD_DACS1_REG 0x65<<11
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@ -2,6 +2,7 @@
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#include "gitInfoGotthard.h"
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#include "versionAPI.h"
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#include "logger.h"
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#include "RegisterDefs.h"
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#ifndef VIRTUAL
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#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
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@ -11,6 +12,8 @@
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#include <time.h>
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#endif
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#include "string.h"
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// Variables that will be exported
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int phaseShift = DEFAULT_PHASE_SHIFT;
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@ -27,7 +30,7 @@ int highvoltage = 0;
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int detectorFirstServer = 1;
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int dacValues[NDAC] = {0};
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enum detectorSettings thisSettings = UNITIALIZED;
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enum detectorSettings thisSettings = UNINITIALIZED;
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enum externalSignalFlag signalMode = 0;
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int digitalTestBit = 0;
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@ -129,7 +132,7 @@ int checkType() {
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#ifdef VIRTUAL
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return OK;
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#endif
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volatile u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MASK) >> DETECTOR_TYPE_OFFSET);
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volatile u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
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if (type == DETECTOR_TYPE_MOENCH_VAL){
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FILE_LOG(logERROR, ("This is not a Gotthard Server (read %d, expected ?)\n", type));
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return FAIL;
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@ -342,7 +345,7 @@ u_int32_t getBoardRevision() {
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#ifdef VIRTUAL
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return 0;
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#endif
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return ((bus_r(BOARD_REVISION_REG) & BOARD_REVISION_MASK) >> BOARD_REVISION_OFST);
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return ((bus_r(BOARD_REVISION_REG) & BOARD_REVISION_MSK) >> BOARD_REVISION_OFST);
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}
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@ -425,7 +428,7 @@ uint32_t readRegister16And32(uint32_t offset) {
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if ((addr == CONTROL_REG) || (addr == FIFO_DATA_REG)) {
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return (u_int32_t)bus_r16(addr);
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} else
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readRegister(offset);
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return readRegister(offset);
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}
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/* firmware functions (resets) */
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@ -553,10 +556,13 @@ int readConfigFile() {
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// Initialization
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const size_t lineSize = 256;
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char line[lineSize] = {0};
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char line[lineSize];
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memset(line, 0, lineSize);
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const size_t keySize = lineSize / 2;
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char key[keySize] = {0};
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char value[keySize] = {0};
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char key[keySize];
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memset(key, 0, keySize);
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char value[keySize];
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memset(value, 0, keySize);
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int scan = OK;
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// keep reading a line
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@ -655,10 +661,10 @@ void setMasterSlaveConfiguration() {
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// master configuration
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if (masterflags == IS_MASTER) {
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// master default delay set, so reset delay
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setDelay(0);
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setTimer(DELAY_AFTER_TRIGGER, 0);
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// Set pattern phase for the master module
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val = (bus_r(MULTI_PURPOSE_REG) & (~(PLL_CLK_SL_MSK))); // unset mask
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u_int32_t val = (bus_r(MULTI_PURPOSE_REG) & (~(PLL_CLK_SL_MSK))); // unset mask
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bus_w(MULTI_PURPOSE_REG, val | PLL_CLK_SL_MSTR_VAL);
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setPhaseShift(patternphase);
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@ -685,7 +691,7 @@ void setMasterSlaveConfiguration() {
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}
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// all configuration - Set RST to SW1 delay
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val = (bus_r(MULTI_PURPOSE_REG) & (~(RST_TO_SW1_DLY_MSK))); // unset mask
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u_int32_t val = (bus_r(MULTI_PURPOSE_REG) & (~(RST_TO_SW1_DLY_MSK))); // unset mask
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val = val | ((rsttosw1delay << RST_TO_SW1_DLY_OFST) & RST_TO_SW1_DLY_MSK); // set val
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bus_w(MULTI_PURPOSE_REG, val);
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FILE_LOG(logDEBUG1, ("\tMultipurpose reg: 0x%x\n", val));
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@ -833,8 +839,8 @@ int64_t setTimer(enum timerIndex ind, int64_t val) {
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if(val >= 0){
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FILE_LOG(logINFO, ("Setting delay: %lldns\n", (long long int)val));
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if (masterflags == IS_MASTER) {
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value += masterdefaultdelay;
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FILE_LOG(logINFO, ("\tActual delay (master): %lld\n", (long long int) value));
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val += masterdefaultdelay;
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FILE_LOG(logINFO, ("\tActual delay (master): %lld\n", (long long int) val));
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}
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val = (val * 1E-3 * CLK_FREQ) + 0.5;
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}
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@ -987,7 +993,7 @@ enum detectorSettings setSettings(enum detectorSettings sett){
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// set conf gain
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bus_w(addr, bus_r(addr) & ~GAIN_CONFGAIN_MSK);
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bus_w(addr, bus_r(addr) | GAIN_CONFGAIN_DYNMC_GAIN_VAL);
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FILE_LOG(logINFO, ("\Gain Reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logINFO, ("\tGain Reg: 0x%x\n", bus_r(addr)));
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thisSettings = sett;
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}
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@ -995,10 +1001,7 @@ enum detectorSettings setSettings(enum detectorSettings sett){
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}
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enum detectorSettings getSettings(){
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uint32_t regval = bus_r(GAIN_REG);
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FILE_LOG(logDEBUG1, ("Getting Settings\n Read Gain Register :0x%x\n", val));
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uint32_t val = regval & GAIN_CONFGAIN_MSK;
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switch(val) {
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case GAIN_CONFGAIN_DYNMC_GAIN_VAL:
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@ -1302,7 +1305,6 @@ void setTiming( enum externalCommunicationMode arg){
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FILE_LOG(logERROR, ("Unknown timing mode %d for this detector\n", (int)arg));
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return;
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}
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timingMode = arg;
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}
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}
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@ -1350,11 +1352,11 @@ void calcChecksum(mac_conf* mac, int sourceip, int destip) {
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mac->ip.ip_chksum = 0x0000 ; // pseudo
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mac->ip.ip_sourceip = sourceip;
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mac->ip.ip_destip = destip;
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FILE_log(logDEBUG1, ("\tIP TTL: 0x%x\n", mac_conf_regs->ip.ip_ttl));
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FILE_LOG(logDEBUG1, ("\tIP TTL: 0x%x\n", mac->ip.ip_ttl));
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int count = sizeof(ip);
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int count = sizeof(mac->ip);
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unsigned short *addr;
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addr = (unsigned short*)(&ip); /* warning: assignment from incompatible pointer type */
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addr = (unsigned short*)(&(mac->ip)); /* warning: assignment from incompatible pointer type */
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long int sum = 0;
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while( count > 1 ) {
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@ -1370,7 +1372,7 @@ void calcChecksum(mac_conf* mac, int sourceip, int destip) {
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mac->ip.ip_chksum = checksum;
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}
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int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t sourceip, uint32_t udpport, uint32_t udpport2, int ival) {
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int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t sourceip, uint32_t udpport, uint32_t udpport2) {
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#ifdef VIRTUAL
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return OK;
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#endif
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@ -1405,35 +1407,35 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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FILE_LOG(logINFO, ("\tDest. Port : %d \t\t\t(0x%08x)\n",udpport, udpport));
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// set/ unset the digital test bit
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if (ival)
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if (digitalTestBit)
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bus_w (addr, bus_r(addr) | DGTL_TST_MSK);
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else
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bus_w (addr, bus_r(addr) & ~DGTL_TST_MSK);
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FILE_log(logDEBUG1, ("\tDigital Test Bit. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tDigital Test Bit. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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//reset mac
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bus_w (addr, bus_r(addr) | RST_MSK);
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FILE_log(logDEBUG1, ("\tReset Mac. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tReset Mac. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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usleep(500000);
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// release reset
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bus_w(addr, bus_r(addr) &(~ RST_MSK));
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FILE_log(logDEBUG1, ("\tReset released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tReset released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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// write shadow regs
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bus_w(addr, bus_r(addr) | (ENT_RSTN_MSK | WRT_BCK_MSK));
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FILE_log(logDEBUG1, ("\tWrite shadow regs. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tWrite shadow regs. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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// release write back
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bus_w(addr, bus_r(addr) &(~WRT_BCK_MSK));
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FILE_log(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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// nreset phy /*FIXME: is this needed ?? */
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bus_w(addr, bus_r(addr) | ENT_RSTN_MSK);
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FILE_log(logDEBUG1, ("\tNreset phy. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tNreset phy. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_log(logDEBUG1, ("\tConfiguring MAC CONF\n"));
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FILE_LOG(logDEBUG1, ("\tConfiguring MAC CONF\n"));
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mac_conf *mac_conf_regs = (mac_conf*)(CSP0BASE + ENET_CONF_REG * 2); // direct write
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mac_conf_regs->mac.mac_dest_mac1 = ((destmac >> (8 * 5)) & 0xFF);
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mac_conf_regs->mac.mac_dest_mac2 = ((destmac >> (8 * 4)) & 0xFF);
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@ -1441,7 +1443,7 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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mac_conf_regs->mac.mac_dest_mac4 = ((destmac >> (8 * 2)) & 0xFF);
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mac_conf_regs->mac.mac_dest_mac5 = ((destmac >> (8 * 1)) & 0xFF);
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mac_conf_regs->mac.mac_dest_mac6 = ((destmac >> (8 * 0)) & 0xFF);
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FILE_log(logDEBUG1, ("\tDestination Mac: %llx %x:%x:%x:%x:%x:%x\n",
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FILE_LOG(logDEBUG1, ("\tDestination Mac: %llx %x:%x:%x:%x:%x:%x\n",
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destmac,
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mac_conf_regs->mac.mac_dest_mac1,
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mac_conf_regs->mac.mac_dest_mac2,
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@ -1455,7 +1457,7 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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mac_conf_regs->mac.mac_src_mac4 = ((sourcemac >> (8 * 2)) & 0xFF);
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mac_conf_regs->mac.mac_src_mac5 = ((sourcemac >> (8 * 1)) & 0xFF);
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mac_conf_regs->mac.mac_src_mac6 = ((sourcemac >> (8 * 0)) & 0xFF);
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FILE_log(logDEBUG1, ("\tSource Mac: %llx %x:%x:%x:%x:%x:%x\n",
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FILE_LOG(logDEBUG1, ("\tSource Mac: %llx %x:%x:%x:%x:%x:%x\n",
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sourcemac,
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mac_conf_regs->mac.mac_src_mac1,
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mac_conf_regs->mac.mac_src_mac2,
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@ -1471,7 +1473,7 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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mac_conf_regs->udp.udp_len = udpPacketSize;
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mac_conf_regs->udp.udp_chksum = 0x0000;
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FILE_log(logDEBUG1, ("\tConfiguring TSE\n"));
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FILE_LOG(logDEBUG1, ("\tConfiguring TSE\n"));
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tse_conf *tse_conf_regs = (tse_conf*)(CSP0BASE + TSE_CONF_REG * 2); // direct write
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tse_conf_regs->rev = 0xA00;
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tse_conf_regs->scratch = 0xCCCCCCCC;
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@ -1491,22 +1493,22 @@ int configureMAC(uint32_t destip, uint64_t destmac, uint64_t sourcemac, uint32_t
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tse_conf_regs->mdio_addr0 = 0x12;
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tse_conf_regs->mdio_addr1 = 0x0;
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FILE_log(logDEBUG1, ("\tConfigure Mac Done"));
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FILE_LOG(logDEBUG1, ("\tConfigure Mac Done"));
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mac_conf_regs->cdone = 0xFFFFFFFF;
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// write shadow regs /* FIXME: Only INT_RSTN_MSK | WRT_BCK_MSK */
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bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK| WRT_BCK_MSK));
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FILE_log(logDEBUG1, ("\tWrite shadow regs with int reset. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tWrite shadow regs with int reset. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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usleep(100000);
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// release write back
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bus_w(addr, bus_r(addr) &(~WRT_BCK_MSK));
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FILE_log(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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FILE_LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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// sw1 /* FIXME: Only SW1_MSK */
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bus_w(addrr, bus_r(addrr) | (INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK));
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FILE_log(logDEBUG1, ("\tSw1. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK));
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FILE_LOG(logDEBUG1, ("\tSw1. MultiPurpose reg: 0x%x\n", bus_r(addr)));
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usleep(1000 * 1000);
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return OK;
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@ -1528,12 +1530,12 @@ void loadImage(enum imageType index, short int imageVals[]){
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volatile u_int16_t *ptr = (u_int16_t*)(CSP0BASE + addr * 2);
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memcpy((char*)ptr, (char*)imageVals, dataBytes);
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FILE_log(logINFO, ("Loaded %s image at 0x%p\n",
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FILE_LOG(logINFO, ("Loaded %s image at 0x%p\n",
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(index == GAIN_IMAGE) ? "Gain" : "Dark", (void*) ptr));
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}
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int readCounterBlock(int startACQ, short int counterVals[]){
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FILE_log(logINFO, ("Reading Counter Block with start Acq :%d\n", startACQ));
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FILE_LOG(logINFO, ("Reading Counter Block with start Acq :%d\n", startACQ));
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// stop any current acquisition
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if (runBusy()) {
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@ -1542,11 +1544,11 @@ int readCounterBlock(int startACQ, short int counterVals[]){
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// waiting for the last frame read to be done
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while(runBusy())
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usleep(500);
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FILE_log(logDEBUG1, ("State machine stopped\n"));
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FILE_LOG(logDEBUG1, ("State machine stopped\n"));
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}
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// copy memory
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addr = COUNTER_MEMORY_REG;
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u_int32_t addr = COUNTER_MEMORY_REG;
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volatile u_int16_t *ptr = (u_int16_t*)(CSP0BASE + addr * 2);
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int dataBytes = calculateDataBytes();
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memcpy((char*)counterVals, (char*)ptr, dataBytes);
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@ -1569,7 +1571,7 @@ int readCounterBlock(int startACQ, short int counterVals[]){
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}
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int resetCounterBlock(int startACQ){
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FILE_log(logINFO, ("Resetting Counter Block with start Acq :%d\n", startACQ));
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FILE_LOG(logINFO, ("Resetting Counter Block with start Acq :%d\n", startACQ));
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// stop any current acquisition
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if (runBusy()) {
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@ -1578,7 +1580,7 @@ int resetCounterBlock(int startACQ){
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// waiting for the last frame read to be done
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while(runBusy())
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usleep(500);
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FILE_log(logDEBUG1, ("State machine stopped\n"));
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FILE_LOG(logDEBUG1, ("State machine stopped\n"));
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}
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// reset counter
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@ -1,5 +1,6 @@
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#pragma once
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#include "sls_detector_defs.h" //default dynamicgain in settings
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#include "sls_detector_defs.h"
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#include <stdlib.h>
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#define GOODBYE (-200)
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