Dev/reg bit change no validate (#970)

- do not validate write reg, setbit and clearbit by default anymore
- --validate will force validation on the bitmask or entire reg
- remove return value for write reg (across server to client, but thankfully not in the Detector class)
- extend validation into writereg, setbit and clearbit for Eiger (always special)
-  need to check python (TODO)
- missed the rx_zmqip implementations in detector.h and python bindings
This commit is contained in:
2024-09-30 16:54:12 +02:00
committed by GitHub
parent a44ba4dc35
commit 2dc0963c56
33 changed files with 499 additions and 171 deletions

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@ -1251,7 +1251,8 @@ int Feb_Control_Disable16bitConversion(int disable) {
regval &= ~bitmask;
}
if (!Feb_Control_WriteRegister_BitMask(DAQ_REG_HRDWRE, regval, bitmask)) {
if (!Feb_Control_WriteRegister_BitMask(DAQ_REG_HRDWRE, regval, bitmask,
1)) {
LOG(logERROR, ("Could not %s 16 bit expansion (bit mode)\n",
(disable ? "disable" : "enable")));
return 0;
@ -1637,7 +1638,7 @@ int Feb_Control_SetChipSignalsToTrimQuad(int enable) {
regval &= ~(DAQ_REG_HRDWRE_PROGRAM_MSK | DAQ_REG_HRDWRE_M8_MSK);
}
if (!Feb_Control_WriteRegister(righOffset, regval)) {
if (!Feb_Control_WriteRegister(righOffset, regval, 1)) {
LOG(logERROR, ("Could not set chip signals to trim quad\n"));
return 0;
}
@ -1666,8 +1667,10 @@ int Feb_Control_GetReadNRows() {
return regVal;
}
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
return Feb_Control_WriteRegister_BitMask(offset, data, BIT32_MSK);
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data, int validate) {
if (!Feb_Control_WriteRegister_BitMask(offset, data, BIT32_MSK, validate))
return 0;
return 1;
}
int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
@ -1675,7 +1678,7 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
}
int Feb_Control_WriteRegister_BitMask(uint32_t offset, uint32_t data,
uint32_t bitmask) {
uint32_t bitmask, int validate) {
uint32_t actualOffset = offset;
char side[2][10] = {"right", "left"};
unsigned int addr[2] = {Feb_Control_rightAddress, Feb_Control_leftAddress};
@ -1720,21 +1723,24 @@ int Feb_Control_WriteRegister_BitMask(uint32_t offset, uint32_t data,
writeVal, side[iloop], actualOffset));
return 0;
}
writeVal &= bitmask;
uint32_t readVal = 0;
if (!Feb_Interface_ReadRegister(addr[iloop], actualOffset,
&readVal)) {
return 0;
}
readVal &= bitmask;
if (validate) {
if (writeVal != readVal) {
LOG(logERROR,
("Could not write %s addr 0x%x register. Wrote "
"0x%x, read 0x%x (mask:0x%x)\n",
side[iloop], actualOffset, writeVal, readVal, bitmask));
return 0;
uint32_t readVal = 0;
if (!Feb_Interface_ReadRegister(addr[iloop], actualOffset,
&readVal)) {
return 0;
}
readVal &= bitmask;
writeVal &= bitmask;
if (writeVal != readVal) {
LOG(logERROR,
("Could not write %s addr 0x%x register. Wrote "
"0x%x, read 0x%x (mask:0x%x)\n",
side[iloop], actualOffset, writeVal, readVal,
bitmask));
return 0;
}
}
}
}

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@ -93,10 +93,10 @@ int Feb_Control_SetQuad(int val);
int Feb_Control_SetChipSignalsToTrimQuad(int enable);
int Feb_Control_SetReadNRows(int value);
int Feb_Control_GetReadNRows();
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data, int validate);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval);
int Feb_Control_WriteRegister_BitMask(uint32_t offset, uint32_t data,
uint32_t bitmask);
uint32_t bitmask, int validate);
int Feb_Control_ReadRegister_BitMask(uint32_t offset, uint32_t *retval,
uint32_t bitmask);
// pulsing

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@ -883,12 +883,12 @@ int setDefaultDac(enum DACINDEX index, enum detectorSettings sett, int value) {
}
/* advanced read/write reg */
int writeRegister(uint32_t offset, uint32_t data) {
int writeRegister(uint32_t offset, uint32_t data, int validate) {
#ifdef VIRTUAL
return OK;
#else
sharedMemory_lockLocalLink();
if (!Feb_Control_WriteRegister(offset, data)) {
if (!Feb_Control_WriteRegister(offset, data, validate)) {
sharedMemory_unlockLocalLink();
return FAIL;
}
@ -911,7 +911,7 @@ int readRegister(uint32_t offset, uint32_t *retval) {
#endif
}
int setBit(const uint32_t addr, const int nBit) {
int setBit(const uint32_t addr, const int nBit, int validate) {
#ifndef VIRTUAL
uint32_t regval = 0;
if (readRegister(addr, &regval) == FAIL) {
@ -921,7 +921,7 @@ int setBit(const uint32_t addr, const int nBit) {
uint32_t val = regval | bitmask;
sharedMemory_lockLocalLink();
if (!Feb_Control_WriteRegister_BitMask(addr, val, bitmask)) {
if (!Feb_Control_WriteRegister_BitMask(addr, val, bitmask, validate)) {
sharedMemory_unlockLocalLink();
return FAIL;
}
@ -930,7 +930,7 @@ int setBit(const uint32_t addr, const int nBit) {
return OK;
}
int clearBit(const uint32_t addr, const int nBit) {
int clearBit(const uint32_t addr, const int nBit, int validate) {
#ifndef VIRTUAL
uint32_t regval = 0;
if (readRegister(addr, &regval) == FAIL) {
@ -940,7 +940,7 @@ int clearBit(const uint32_t addr, const int nBit) {
uint32_t val = regval & ~bitmask;
sharedMemory_lockLocalLink();
if (!Feb_Control_WriteRegister_BitMask(addr, val, bitmask)) {
if (!Feb_Control_WriteRegister_BitMask(addr, val, bitmask, validate)) {
sharedMemory_unlockLocalLink();
return FAIL;
}

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@ -527,12 +527,12 @@ int setDefaultDac(enum DACINDEX index, enum detectorSettings sett, int value) {
return OK;
}
uint32_t writeRegister16And32(uint32_t offset, uint32_t data) {
void writeRegister16And32(uint32_t offset, uint32_t data) {
if (((offset << MEM_MAP_SHIFT) == CONTROL_REG) ||
((offset << MEM_MAP_SHIFT) == FIFO_DATA_REG)) {
return writeRegister16(offset, data);
writeRegister16(offset, data);
} else
return writeRegister(offset, data);
writeRegister(offset, data);
}
uint32_t readRegister16And32(uint32_t offset) {

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@ -81,7 +81,7 @@ u_int32_t readRegister(u_int32_t offset);
* @param offset address offset
* @param data 32 bit data
*/
u_int32_t writeRegister(u_int32_t offset, u_int32_t data);
void writeRegister(u_int32_t offset, u_int32_t data);
/**
* Read from a 16 bit register (literal register value provided by client)
@ -95,7 +95,7 @@ u_int32_t readRegister16(u_int32_t offset);
* @param offset address offset
* @param data 16 bit data
*/
u_int32_t writeRegister16(u_int32_t offset, u_int32_t data);
void writeRegister16(u_int32_t offset, u_int32_t data);
/**
* Get base address for memory copy

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@ -78,7 +78,7 @@ u_int32_t readRegister(u_int32_t offset);
* @param offset address offset
* @param data 32 bit data
*/
u_int32_t writeRegister(u_int32_t offset, u_int32_t data);
void writeRegister(u_int32_t offset, u_int32_t data);
/**
* Map FPGA

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@ -172,14 +172,13 @@ void resetToHardwareSettings();
// advanced read/write reg
#ifdef EIGERD
int writeRegister(uint32_t offset, uint32_t data);
int writeRegister(uint32_t offset, uint32_t data, int validate);
int readRegister(uint32_t offset, uint32_t *retval);
int setBit(const uint32_t addr, int nBit);
int clearBit(const uint32_t addr, int nBit);
int setBit(const uint32_t addr, const int nBit, int validate);
int clearBit(const uint32_t addr, const int nBit, int validate);
int getBit(const uint32_t addr, const int nBit, int *retval);
#elif GOTTHARDD
uint32_t writeRegister16And32(uint32_t offset,
uint32_t data); // FIXME its not there in ctb
void writeRegister16And32(uint32_t offset, uint32_t data);
uint32_t readRegister16And32(uint32_t offset);
#endif

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@ -84,7 +84,7 @@ u_int32_t readRegister(u_int32_t offset) {
return bus_r(offset << MEM_MAP_SHIFT);
}
u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
void writeRegister(u_int32_t offset, u_int32_t data) {
// if electron mode bit touched
#ifdef JUNGFRAUD
int electronCollectionModeChange = 0;
@ -100,16 +100,14 @@ u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
configureChip();
}
#endif
return readRegister(offset);
}
u_int32_t readRegister16(u_int32_t offset) {
return (u_int32_t)bus_r16(offset << MEM_MAP_SHIFT);
}
u_int32_t writeRegister16(u_int32_t offset, u_int32_t data) {
void writeRegister16(u_int32_t offset, u_int32_t data) {
bus_w16(offset << MEM_MAP_SHIFT, (u_int16_t)data);
return readRegister16(offset);
}
int mapCSP0(void) {

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@ -82,10 +82,7 @@ void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
u_int32_t readRegister(u_int32_t offset) { return bus_r(offset); }
u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
bus_w(offset, data);
return readRegister(offset);
}
void writeRegister(u_int32_t offset, u_int32_t data) { bus_w(offset, data); }
int mapCSP0(void) {
u_int32_t csps[2] = {CSP0, CSP1};

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@ -1649,40 +1649,35 @@ int get_adc(int file_des) {
int write_register(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
uint32_t args[2] = {-1, -1};
uint32_t retval = -1;
uint32_t args[3] = {-1, -1, -1};
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
uint32_t addr = args[0];
uint32_t val = args[1];
LOG(logDEBUG1, ("Writing to register 0x%x, data 0x%x\n", addr, val));
uint32_t validate = args[2];
LOG(logDEBUG1, ("Writing to register 0x%x, data 0x%x, validate:%d\n", addr,
val, validate));
// only set
if (Server_VerifyLock() == OK) {
#ifdef GOTTHARDD
retval = writeRegister16And32(addr, val);
#elif EIGERD
if (writeRegister(addr, val) == FAIL) {
#if EIGERD
if (writeRegister(addr, val, validate) == FAIL) {
ret = FAIL;
sprintf(mess, "Could not write to register 0x%x.\n", addr);
LOG(logERROR, (mess));
} else {
if (readRegister(addr, &retval) == FAIL) {
ret = FAIL;
sprintf(
mess,
"Could not read register 0x%x or inconsistent values. Try "
"to read +0x100 for only left and +0x200 for only right.\n",
addr);
LOG(logERROR, (mess));
}
}
#else
retval = writeRegister(addr, val);
#ifdef GOTTHARDD
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr);
#else
writeRegister(addr, val);
uint32_t retval = readRegister(addr);
#endif
LOG(logDEBUG1, ("Write register retval (0x%x): 0x%x\n", addr, retval));
// validate
if (ret == OK && retval != val) {
if (validate && ret == OK && retval != val) {
ret = FAIL;
sprintf(
mess,
@ -1690,9 +1685,9 @@ int write_register(int file_des) {
addr, val, retval);
LOG(logERROR, (mess));
}
LOG(logDEBUG1, ("Write register (0x%x): 0x%x\n", retval));
#endif
}
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
return Server_SendResult(file_des, INT32, NULL, 0);
}
int read_register(int file_des) {
@ -1707,9 +1702,7 @@ int read_register(int file_des) {
LOG(logDEBUG1, ("Reading from register 0x%x\n", addr));
// get
#ifdef GOTTHARDD
retval = readRegister16And32(addr);
#elif EIGERD
#if EIGERD
if (readRegister(addr, &retval) == FAIL) {
ret = FAIL;
sprintf(mess,
@ -1718,6 +1711,8 @@ int read_register(int file_des) {
addr);
LOG(logERROR, (mess));
}
#elif GOTTHARDD
retval = readRegister16And32(addr);
#else
retval = readRegister(addr);
#endif
@ -10594,13 +10589,15 @@ int get_frontend_firmware_version(int file_des) {
int set_bit(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
uint32_t args[2] = {-1, -1};
uint32_t args[3] = {-1, -1, -1};
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
uint32_t addr = args[0];
int nBit = (int)args[1];
LOG(logDEBUG1, ("Setting bit %d of reg 0x%x\n", nBit, addr));
uint32_t validate = args[2];
LOG(logDEBUG1,
("Setting bit %d of reg 0x%x, validate:%d\n", nBit, addr, validate));
// only set
if (Server_VerifyLock() == OK) {
@ -10613,20 +10610,23 @@ int set_bit(int file_des) {
LOG(logERROR, (mess));
} else {
#ifdef EIGERD
ret = setBit(addr, nBit);
if (ret == FAIL) {
ret = setBit(addr, nBit, validate);
#else
uint32_t bitmask = (1 << nBit);
#ifdef GOTTHARDD
uint32_t val = readRegister16And32(addr) | bitmask;
uint32_t retval = writeRegister16And32(addr, val);
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr) | bitmask;
#else
uint32_t val = readRegister(addr) | bitmask;
uint32_t retval = writeRegister(addr, val);
writeRegister(addr, val);
uint32_t retval = readRegister(addr) | bitmask;
#endif
if (!(retval & bitmask)) {
if (validate && (!(retval & bitmask))) {
ret = FAIL;
}
#endif
if (ret == FAIL) {
sprintf(mess, "Could not set bit %d.\n", nBit);
LOG(logERROR, (mess));
}
@ -10638,13 +10638,15 @@ int set_bit(int file_des) {
int clear_bit(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
uint32_t args[2] = {-1, -1};
uint32_t args[3] = {-1, -1, -1};
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
uint32_t addr = args[0];
int nBit = (int)args[1];
LOG(logDEBUG1, ("Clearing bit %d of reg 0x%x\n", nBit, addr));
uint32_t validate = args[2];
LOG(logDEBUG1,
("Clearing bit %d of reg 0x%x, validate:%d\n", nBit, addr, validate));
// only set
if (Server_VerifyLock() == OK) {
@ -10657,20 +10659,23 @@ int clear_bit(int file_des) {
LOG(logERROR, (mess));
} else {
#ifdef EIGERD
ret = clearBit(addr, nBit);
if (ret == FAIL) {
ret = clearBit(addr, nBit, validate);
#else
uint32_t bitmask = (1 << nBit);
#ifdef GOTTHARDD
uint32_t val = readRegister16And32(addr) & ~bitmask;
uint32_t retval = writeRegister16And32(addr, val);
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr) & ~bitmask;
#else
uint32_t val = readRegister(addr) & ~bitmask;
uint32_t retval = writeRegister(addr, val);
writeRegister(addr, val);
uint32_t retval = readRegister(addr) & ~bitmask;
#endif
if (retval & bitmask) {
if (validate && (retval & bitmask)) {
ret = FAIL;
}
#endif
if (ret == FAIL) {
sprintf(mess, "Could not clear bit %d.\n", nBit);
LOG(logERROR, (mess));
}