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ctb: add patternstart command, xilinx: fix frequency (#1307)
* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command * update docs * Dhanya's comments * more Dhanya comments * refactored * fixed tests for startpatttern, also clkfrequency not properly used in server * xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value * xilinx freq in kHz, updated default values and prints --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
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@@ -72,14 +72,14 @@
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// clang-format on
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// freq in kHz !!
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void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
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int XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
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if (clk_index >= XILINX_PLL_NUM_CLKS) {
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LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
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return;
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return 1;
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}
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if (freq < XILINX_PLL_MIN_FREQ || freq > XILINX_PLL_MAX_FREQ) {
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LOG(logERROR, ("XILINX_PLL: Frequency %d kHz is out of range\n", freq));
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return;
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return 1;
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}
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// calculate base clock frequency
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@@ -103,7 +103,7 @@ void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
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if (clk_div < 1 || clk_div > XILINX_PLL_MAX_CLK_DIV) {
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LOG(logERROR,
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("XILINX_PLL: Invalid clock divider, need to change base clock\n"));
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return;
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return 1;
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}
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uint32_t clk_div_frac = 0;
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@@ -140,18 +140,19 @@ void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
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// wait for firmware to measure the actual frequency
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usleep(2 * 1000 * 1000);
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return 0;
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}
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uint32_t XILINX_PLL_getFrequency(uint32_t clk_index) {
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if (clk_index >= XILINX_PLL_NUM_CLKS) {
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LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
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return 0;
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return -1;
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}
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if (clk_index > XILINX_PLL_MAX_NUM_CLKS_FOR_GET) {
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LOG(logERROR,
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("XILINX_PLL: get frequency not implemented for this clock %d\n",
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clk_index));
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return 0;
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return -1;
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}
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uint32_t base_addr = XILINX_PLL_MEASURE_BASE_ADDR0;
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