ctb: add patternstart command, xilinx: fix frequency (#1307)
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* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command

* update docs

* Dhanya's comments

* more Dhanya comments

* refactored

* fixed tests for startpatttern, also clkfrequency not properly used in server

* xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value

* xilinx freq in kHz, updated default values and prints

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
This commit is contained in:
Martin Mueller
2025-09-23 12:13:46 +02:00
committed by GitHub
parent e7a91d38f2
commit 2d8f93a426
17 changed files with 124 additions and 59 deletions

View File

@@ -72,14 +72,14 @@
// clang-format on
// freq in kHz !!
void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
int XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return;
return 1;
}
if (freq < XILINX_PLL_MIN_FREQ || freq > XILINX_PLL_MAX_FREQ) {
LOG(logERROR, ("XILINX_PLL: Frequency %d kHz is out of range\n", freq));
return;
return 1;
}
// calculate base clock frequency
@@ -103,7 +103,7 @@ void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
if (clk_div < 1 || clk_div > XILINX_PLL_MAX_CLK_DIV) {
LOG(logERROR,
("XILINX_PLL: Invalid clock divider, need to change base clock\n"));
return;
return 1;
}
uint32_t clk_div_frac = 0;
@@ -140,18 +140,19 @@ void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
// wait for firmware to measure the actual frequency
usleep(2 * 1000 * 1000);
return 0;
}
uint32_t XILINX_PLL_getFrequency(uint32_t clk_index) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return 0;
return -1;
}
if (clk_index > XILINX_PLL_MAX_NUM_CLKS_FOR_GET) {
LOG(logERROR,
("XILINX_PLL: get frequency not implemented for this clock %d\n",
clk_index));
return 0;
return -1;
}
uint32_t base_addr = XILINX_PLL_MEASURE_BASE_ADDR0;