ctb: add patternstart command, xilinx: fix frequency (#1307)
Some checks failed
Build on RHEL9 / build (push) Failing after 3m9s
Build on RHEL8 / build (push) Failing after 5m11s

* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command

* update docs

* Dhanya's comments

* more Dhanya comments

* refactored

* fixed tests for startpatttern, also clkfrequency not properly used in server

* xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value

* xilinx freq in kHz, updated default values and prints

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
This commit is contained in:
Martin Mueller
2025-09-23 12:13:46 +02:00
committed by GitHub
parent e7a91d38f2
commit 2d8f93a426
17 changed files with 124 additions and 59 deletions

View File

@@ -72,14 +72,14 @@
// clang-format on
// freq in kHz !!
void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
int XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return;
return 1;
}
if (freq < XILINX_PLL_MIN_FREQ || freq > XILINX_PLL_MAX_FREQ) {
LOG(logERROR, ("XILINX_PLL: Frequency %d kHz is out of range\n", freq));
return;
return 1;
}
// calculate base clock frequency
@@ -103,7 +103,7 @@ void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
if (clk_div < 1 || clk_div > XILINX_PLL_MAX_CLK_DIV) {
LOG(logERROR,
("XILINX_PLL: Invalid clock divider, need to change base clock\n"));
return;
return 1;
}
uint32_t clk_div_frac = 0;
@@ -140,18 +140,19 @@ void XILINX_PLL_setFrequency(uint32_t clk_index, uint32_t freq) {
// wait for firmware to measure the actual frequency
usleep(2 * 1000 * 1000);
return 0;
}
uint32_t XILINX_PLL_getFrequency(uint32_t clk_index) {
if (clk_index >= XILINX_PLL_NUM_CLKS) {
LOG(logERROR, ("XILINX_PLL: Invalid clock index %d\n", clk_index));
return 0;
return -1;
}
if (clk_index > XILINX_PLL_MAX_NUM_CLKS_FOR_GET) {
LOG(logERROR,
("XILINX_PLL: get frequency not implemented for this clock %d\n",
clk_index));
return 0;
return -1;
}
uint32_t base_addr = XILINX_PLL_MEASURE_BASE_ADDR0;

View File

@@ -623,28 +623,43 @@ uint64_t getPatternBitMask() {
return getU64BitReg(PATTERN_SET_LSB_REG, PATTERN_SET_MSB_REG);
}
#ifdef MYTHEN3D
void startPattern() {
LOG(logINFOBLUE, ("Starting Pattern\n"));
#ifdef MYTHEN3D
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_PATTERN_MSK);
usleep(1);
while (bus_r(PAT_STATUS_REG) & PAT_STATUS_RUN_BUSY_MSK) {
usleep(1);
}
LOG(logINFOBLUE, ("Pattern done\n"));
}
#endif
#ifdef XILINX_CHIPTESTBOARDD
void startPattern() {
LOG(logINFOBLUE, ("Starting Pattern\n"));
#elif CHIPTESTBOARDD
// we only want to run the pattern here. No acquisition, no UDP packets
// disable 10G UDP temporarily
// except if the pattern explicitly contains udp trigger points
uint32_t conf_reg_tmp = bus_r(CONFIG_REG);
if ((bus_r(STREAMING_CTRL_REG) & STREAMING_CTRL_ENA_MSK) == 0) {
bus_w(CONFIG_REG, conf_reg_tmp & ~CONFIG_GB10_SND_UDP_MSK);
}
// run the pattern, wait till done
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STRT_ACQSTN_MSK);
bus_w(CONTROL_REG, bus_r(CONTROL_REG) & ~CONTROL_STRT_ACQSTN_MSK);
usleep(1);
while (bus_r(STATUS_REG) & STATUS_RN_BSY_MSK) {
usleep(1);
}
// go back to original config
bus_w(CONFIG_REG, conf_reg_tmp);
#elif XILINX_CHIPTESTBOARDD
bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
usleep(1);
while (bus_r(FLOW_CONTROL_REG) & RSM_BUSY_MSK) {
usleep(1);
}
#endif
LOG(logINFOBLUE, ("Pattern done\n"));
}
#endif
char *getPatternFileName() { return clientPatternfile; }

View File

@@ -5839,15 +5839,24 @@ int set_clock_frequency(int file_des) {
LOG(logINFO, ("Same %s: %d %s\n", modeName, val,
myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
} else {
setFrequency(c, val);
int retval = getFrequency(c);
LOG(logDEBUG1, ("retval %s: %d %s\n", modeName, retval,
myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
#if !defined( \
XILINX_CHIPTESTBOARDD) // XCTB will give the actual frequency, which is not
// 100% identical to the set frequency
validate(&ret, mess, val, retval, modeName, DEC);
int ret = setFrequency(c, val);
if (ret == FAIL) {
sprintf(mess, "Could not set %s to %d %s\n", modeName, val,
myDetectorType == XILINX_CHIPTESTBOARD ? "kHz"
: "MHz");
LOG(logERROR, (mess));
} else {
int retval = getFrequency(c);
LOG(logDEBUG1,
("retval %s: %d %s\n", modeName, retval,
myDetectorType == XILINX_CHIPTESTBOARD ? "kHz"
: "MHz"));
#if !defined(XILINX_CHIPTESTBOARDD)
// XCTB will give the actual frequency, which is not
// 100% identical to the set frequency
validate(&ret, mess, val, retval, modeName, DEC);
#endif
}
}
}
}
@@ -5902,8 +5911,11 @@ int get_clock_frequency(int file_des) {
LOG(logDEBUG1,
("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c,
retval,
myDetectorType == GOTTHARD2 || myDetectorType == MYTHEN3 ? "Hz"
: "MHz"));
myDetectorType == XILINX_CHIPTESTBOARD
? "kHz"
: (myDetectorType == GOTTHARD2 || myDetectorType == MYTHEN3
? "Hz"
: "MHz")));
}
#endif
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
@@ -7468,7 +7480,8 @@ int start_pattern(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Starting Pattern\n"));
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD)
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) && \
!defined(CHIPTESTBOARDD)
functionNotImplemented();
#else
// only set