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jungfrau board 2 adc defines, full speed limitation for old boards

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This commit is contained in:
maliakal_d
2019-05-27 15:04:13 +02:00
parent 7fdab08256
commit 2c2fb7358c
7 changed files with 73 additions and 42 deletions
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32
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h
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@ -303,10 +303,9 @@
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
// 1 = full speed, 2 = half speed, 4 = quarter speed
#define SAMPLE_DECMT_FACTOR_1_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_2_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_4_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_FULL_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
/** Vref Comp Mod Register */
#define VREF_COMP_MOD_REG (0x5C << MEM_MAP_SHIFT)
@ -393,45 +392,30 @@
#define SET_TRIGGER_DELAY_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_TRIGGER_DELAY_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Module Coordinates Register 0 */
#define COORD_0_REG (0x7C << MEM_MAP_SHIFT)
#define COORD_0_Y_OFST (0)
#define COORD_0_Y_MSK (0x0000FFFF << COORD_0_Y_OFST)
#define COORD_0_X_OFST (16)
#define COORD_0_X_MSK (0x0000FFFF << COORD_0_X_OFST)
/* Module Coordinates Register 1 */
#define COORD_1_REG (0x7D << MEM_MAP_SHIFT)
#define COORD_0_Z_OFST (0)
#define COORD_0_Z_MSK (0x0000FFFF << COORD_0_Z_OFST)
/** Module row coordinates */
/*#define COORD_ROW_REG (0x7C << MEM_MAP_SHIFT)
#define COORD_ROW_REG (0x7C << MEM_MAP_SHIFT)
#define COORD_ROW_OUTER_OFST (0)
#define COORD_ROW_OUTER_MSK (0x0000FFFF << COORD_ROW_OUTER_OFST)
#define COORD_ROW_INNER_OFST (16)
#define COORD_ROW_INNER_MSK (0x0000FFFF << COORD_ROW_INNER_OFST)
*/
/** Module column coordinates */
/*#define COORD_COL_REG (0x7D << MEM_MAP_SHIFT)
#define COORD_COL_REG (0x7D << MEM_MAP_SHIFT)
#define COORD_COL_OUTER_OFST (0)
#define COORD_COL_OUTER_MSK (0x0000FFFF << COORD_COL_OUTER_OFST)
#define COORD_COL_INNER_OFST (16)
#define COORD_COL_INNER_MSK (0x0000FFFF << COORD_COL_INNER_OFST)
*/
/** Module column coordinates */
/*#define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
#define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
#define COORD_RESERVED_OUTER_OFST (0)
#define COORD_RESERVED_OUTER_MSK (0x0000FFFF << COORD_RESERVED_OUTER_OFST)
#define COORD_RESERVED_INNER_OFST (16)
#define COORD_RESERVED_INNER_MSK (0x0000FFFF << COORD_RESERVED_INNER_OFST)
*/
/* ASIC Control Register */
#define ASIC_CTRL_REG (0x7F << MEM_MAP_SHIFT)