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Dev/remove gotthard i (#1108)

Browse Source 
* slsSupportLib done, at receiver rooting out in implementation

* removed from receiver and client

* removed everywhere except gui, python and client(commands.yaml and Detector.h)

* updated python

* fixed autocomplete to print what the issue is if there is one with ToString when running the autocomplete script to generate fixed.json. updated readme.md in generator folder

* formatting

* removed enums for dacs

* udpating autocomplete and generating commands

* removed gotthard from docs and release notes

* removed dac test

* bug from removing g1

* fixed virtual test for xilinx, was minor. so in this PR

* gui done

* binary in merge fix

* formatting and removing enums

* updated fixed and dump.json

* bash autocomplete

* updated doc on command line generation

* removing increments in dac enums for backward compatibility. Not required

* removed ROI from rxParameters  (only in g1), not needed to be backward compatible

* removed the phase shift option from det server staruip
This commit is contained in:
maliakal_d
2025-03-10 14:24:33 +01:00
committed by GitHub
parent fa504e6675
commit 297c3752e3
103 changed files with 20090 additions and 27262 deletions
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1
slsDetectorServers/CMakeLists.txt
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@ -13,7 +13,6 @@ install(TARGETS slsProjectCSettings
add_subdirectory(ctbDetectorServer)
add_subdirectory(xilinx_ctbDetectorServer)
add_subdirectory(eigerDetectorServer)
add_subdirectory(gotthardDetectorServer)
add_subdirectory(jungfrauDetectorServer)
add_subdirectory(mythen3DetectorServer)
add_subdirectory(gotthard2DetectorServer)

1
slsDetectorServers/compileAllServers.sh
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@ -4,7 +4,6 @@
# empty branch = developer branch in updateAPIVersion.sh
branch=""
det_list=("ctbDetectorServer
gotthardDetectorServer
gotthard2DetectorServer
jungfrauDetectorServer
mythen3DetectorServer

1
slsDetectorServers/compileAllServers_noAPIUpdate.sh
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@ -4,7 +4,6 @@
# empty branch = developer branch in updateAPIVersion.sh
branch=""
det_list=("ctbDetectorServer"
"gotthardDetectorServer"
"gotthard2DetectorServer"
"jungfrauDetectorServer"
"mythen3DetectorServer"

BIN
slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer
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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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1
slsDetectorServers/gotthardDetectorServer/.target-makefrag
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@ -1 +0,0 @@
AXIS_BUILDTYPE ?= cris-axis-linux-gnu

45
slsDetectorServers/gotthardDetectorServer/CMakeLists.txt
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@ -1,45 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
add_executable(gotthardDetectorServer_virtual
slsDetectorFunctionList.c
../slsDetectorServer/src/slsDetectorServer.c
../slsDetectorServer/src/slsDetectorServer_funcs.c
../slsDetectorServer/src/communication_funcs.c
../slsDetectorServer/src/blackfin.c
../slsDetectorServer/src/AD9252.c
../slsDetectorServer/src/AD9257.c
../slsDetectorServer/src/LTC2620.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/commonServerFunctions.c
../slsDetectorServer/src/programViaBlackfin.c
../slsDetectorServer/src/communication_funcs_UDP.c
../slsDetectorServer/src/sharedMemory.c
../../slsSupportLib/src/md5.c
)
include_directories(
../slsDetectorServer/include
../../slsSupportLib/include
)
target_include_directories(gotthardDetectorServer_virtual
PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}
)
target_compile_definitions(gotthardDetectorServer_virtual
PUBLIC GOTTHARDD VIRTUAL STOP_SERVER
)
target_link_libraries(gotthardDetectorServer_virtual
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(gotthardDetectorServer_virtual PROPERTIES
RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin
)
install(TARGETS gotthardDetectorServer_virtual
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
)
configure_file(config_gotthard.txt ${CMAKE_BINARY_DIR}/bin/config_gotthard.txt COPYONLY)

48
slsDetectorServers/gotthardDetectorServer/Makefile
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@ -1,48 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
current_dir = $(shell pwd)
main_inc = ../slsDetectorServer/include/
main_src = ../slsDetectorServer/src/
support_lib = ../../slsSupportLib/include/
md5_dir = ../../slsSupportLib/src/
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -std=gnu99 -DGOTTHARDD -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lrt -pthread
PROGS = gotthardDetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRCS = slsDetectorFunctionList.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)blackfin.c $(main_src)AD9252.c $(main_src)AD9257.c $(main_src)LTC2620.c $(main_src)programViaBlackfin.c $(main_src)common.c $(main_src)commonServerFunctions.c $(main_src)/sharedMemory.c $(md5_dir)md5.c
OBJS = $(SRCS:.c=.o)
all: clean $(PROGS)
version: clean versioning $(PROGS)
boot: $(OBJS)
version_branch=$(API_BRANCH)
version_name=APIGOTTHARD
version_path=slsDetectorServers/gotthardDetectorServer
versioning:
cd ../../ && echo $(PWD) && echo `tput setaf 6; ./updateAPIVersion.sh $(version_name) $(version_path) $(version_branch); tput sgr0;`
$(PROGS): $(OBJS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
cp config_gotthard.txt $(DESTDIR)
rm *.gdb
rm $(main_src)*.o $(md5_dir)*.o
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb $(main_src)*.o $(md5_dir)*.o

394
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h
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@ -1,394 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
/* Definitions for FPGA*/
#define MEM_MAP_SHIFT (11)
/** Gain register */
#define GAIN_REG (0x10 << MEM_MAP_SHIFT)
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL \
((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL \
((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL \
((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL \
((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL \
((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Flow Control register */
// #define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
/** Flow Status register */
// #define FLOW_STATUS_REG (0x12 << MEM_MAP_SHIFT)
/** Frame register */
// #define FRAME_REG (0x13 << MEM_MAP_SHIFT)
/** Multi Purpose register */
#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
#define PHS_STP_OFST (0)
#define PHS_STP_MSK (0x00000001 << PHS_STP_OFST)
#define RST_CNTR_OFST (2)
#define RST_CNTR_MSK (0x00000001 << RST_CNTR_OFST)
#define SW1_OFST (5)
#define SW1_MSK (0x00000001 << SW1_OFST)
#define WRT_BCK_OFST (6)
#define WRT_BCK_MSK (0x00000001 << WRT_BCK_OFST)
#define RST_OFST (7)
#define RST_MSK (0x00000001 << RST_OFST)
#define PLL_CLK_SL_OFST (8)
#define PLL_CLK_SL_MSK (0x00000007 << PLL_CLK_SL_OFST)
#define PLL_CLK_SL_MSTR_VAL ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_MSTR_ADC_VAL ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_VAL ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_ADC_VAL ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define ENT_RSTN_OFST (11)
#define ENT_RSTN_MSK (0x00000001 << ENT_RSTN_OFST)
#define INT_RSTN_OFST (12)
#define INT_RSTN_MSK (0x00000001 << INT_RSTN_OFST)
#define DGTL_TST_OFST (14)
#define DGTL_TST_MSK (0x00000001 << DGTL_TST_OFST)
#define CHNG_AT_PWR_ON_OFST (15) // Not used in SW
#define CHNG_AT_PWR_ON_MSK (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
#define RST_TO_SW1_DLY_OFST (16)
#define RST_TO_SW1_DLY_MSK (0x0000000F << RST_TO_SW1_DLY_OFST)
#define STRT_ACQ_DLY_OFST (20)
#define STRT_ACQ_DLY_MSK (0x0000000F << STRT_ACQ_DLY_OFST)
/** DAQ register */
#define DAQ_REG (0x15 << MEM_MAP_SHIFT)
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL \
((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL \
((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL \
((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL \
((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** Time From Start register */
// #define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
/** DAC Control register */
#define SPI_REG (0x17 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_CS_OTPT_OFST (0)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (2)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
/** ADC SPI register */
#define ADC_SPI_REG (0x18 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000001F << ADC_SPI_SRL_CS_OTPT_OFST)
/** ADC Sync register */
#define ADC_SYNC_REG (0x19 << MEM_MAP_SHIFT)
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL \
((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL \
((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL \
((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL \
((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL \
((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
// 0x32214
#define ADC_SYNC_TKN_VAL \
(ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | \
ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | \
ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL \
((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL \
((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
/** Time From Start register */
// #define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
/** Temperatre SPI In register */
#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
#define TEMP_SPI_IN_T1_CLK_OFST (0)
#define TEMP_SPI_IN_T1_CLK_MSK (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
#define TEMP_SPI_IN_T1_CS_OFST (1)
#define TEMP_SPI_IN_T1_CS_MSK (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
#define TEMP_SPI_IN_T2_CLK_OFST (2)
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
#define TEMP_SPI_IN_IDLE_MSK \
(TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | \
TEMP_SPI_IN_T2_CLK_MSK)
/** Temperatre SPI Out register */
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
#define TEMP_SPI_OUT_T1_DT_OFST (0)
#define TEMP_SPI_OUT_T1_DT_MSK (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
#define TEMP_SPI_OUT_T2_DT_OFST (1)
#define TEMP_SPI_OUT_T2_DT_MSK (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
/** TSE Configure register */
#define TSE_CONF_REG (0x1d << MEM_MAP_SHIFT)
/** SPI Configure register */
#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
/** Write TSE Shadow register */
// #define WRITE_TSE_SHADOW_REG (0x1f << MEM_MAP_SHIFT)
/** High Voltage register */
#define HV_REG (0x20 << MEM_MAP_SHIFT)
#define HV_ENBL_OFST (0)
#define HV_ENBL_MSK (0x00000001 << HV_ENBL_OFST)
#define HV_SEL_OFST (1)
#define HV_SEL_MSK (0x00000007 << HV_SEL_OFST)
#define HV_SEL_90_VAL ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_110_VAL ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_120_VAL ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_150_VAL ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_180_VAL ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_200_VAL ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
/** Dummy register */
#define DUMMY_REG (0x21 << MEM_MAP_SHIFT)
/** Firmware Version register */
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK \
(0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
/* Fix Pattern register */
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC1980)
/** 16 bit Control register */
#define CONTROL_REG (0x24 << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQ_OFST (0)
#define CONTROL_STRT_ACQ_MSK (0x00000001 << CONTROL_STRT_ACQ_OFST)
#define CONTROL_STP_ACQ_OFST (1)
#define CONTROL_STP_ACQ_MSK (0x00000001 << CONTROL_STP_ACQ_OFST)
#define CONTROL_STRT_FF_TST_OFST (2) // Not used in FW & SW
#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
#define CONTROL_STP_FF_TST_OFST (3) // Not used in FW & SW
#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
#define CONTROL_STRT_RDT_OFST (4)
#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
#define CONTROL_STP_RDT_OFST (5)
#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
#define CONTROL_STP_EXPSR_OFST (7)
#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_EXPSR_OFST)
#define CONTROL_STRT_TRN_OFST (8)
#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_TRN_OFST)
#define CONTROL_STP_TRN_OFST (9)
#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_TRN_OFST)
#define CONTROL_SYNC_RST_OFST (10)
#define CONTROL_SYNC_RST_MSK (0x00000001 << CONTROL_SYNC_RST_OFST)
/** Status register */
#define STATUS_REG (0x25 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_RD_STT_OFST (8)
#define STATUS_RD_STT_MSK (0x00000007 << STATUS_RD_STT_OFST)
#define STATUS_RN_STT_OFST (12)
#define STATUS_RN_STT_MSK (0x00000007 << STATUS_RN_STT_OFST)
#define STATUS_SM_FF_FLL_OFST (15)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (11)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_RN_MSHN_BSY_OFST (17)
#define STATUS_RN_MSHN_BSY_MSK (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
#define STATUS_RD_MSHN_BSY_OFST (18)
#define STATUS_RD_MSHN_BSY_MSK (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
#define STATUS_RN_FNSHD_OFST (20)
#define STATUS_RN_FNSHD_MSK (0x00000001 << STATUS_RN_FNSHD_OFST)
#define STATUS_IDLE_MSK (0x0000FFFF << 0)
/** Config register */
#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
#define CONFIG_CPU_RDT_OFST (12)
#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
/** External Signal register */
#define EXT_SIGNAL_REG (0x27 << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL \
((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/** Look at me register */
// #define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
/** FPGA SVN register */
// #define FPGA_SVN_REG (0x29 << MEM_MAP_SHIFT)
/** Chip of Interest register */
#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK \
(0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Out MUX register */
// #define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
/** Board Version register */
#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
#define BOARD_REVISION_OFST (0)
#define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST)
#define DETECTOR_TYPE_OFST (16)
#define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST)
// #define DETECTOR_TYPE_GOTTHARD_VAL (??)
#define DETECTOR_TYPE_MOENCH_VAL (2)
/** Memory Test register */
// #define MEMORY_TEST_REG (0x2d << MEM_MAP_SHIFT)
/** Hit Threshold register */
// #define HIT_THRESHOLD_REG (0x2e << MEM_MAP_SHIFT)
/** Hit Count register */
// #define HIT_COUNT_REG (0x2f << MEM_MAP_SHIFT)
/* 16 bit Fifo Data register */
#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
/** Dacs Set 1 register */
// #define DACS_SET_1_REG (0x65 << MEM_MAP_SHIFT)
/** Dacs Set 2 register */
// #define DACS_SET_2_REG (0x66 << MEM_MAP_SHIFT)
/** Dacs Set 3 register */
// #define DACS_SET_3_REG (0x67 << MEM_MAP_SHIFT)
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_DELAY_MSB_REG (0x69 << MEM_MAP_SHIFT)
/* Get Delay 64 bit register */
#define GET_DELAY_LSB_REG (0x6a << MEM_MAP_SHIFT)
#define GET_DELAY_MSB_REG (0x6b << MEM_MAP_SHIFT)
/* Set Triggers 64 bit register */
#define SET_TRAINS_LSB_REG (0x6c << MEM_MAP_SHIFT)
#define SET_TRAINS_MSB_REG (0x6d << MEM_MAP_SHIFT)
/* Get Triggers 64 bit register */
#define GET_TRAINS_LSB_REG (0x6e << MEM_MAP_SHIFT)
#define GET_TRAINS_MSB_REG (0x6f << MEM_MAP_SHIFT)
/* Set Frames 64 bit register */
#define SET_FRAMES_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Get Frames 64 bit register */
#define GET_FRAMES_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Set Period 64 bit register */
#define SET_PERIOD_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Get Period 64 bit register */
#define GET_PERIOD_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Set Exptime 64 bit register */
#define SET_EXPTIME_LSB_REG (0x78 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x79 << MEM_MAP_SHIFT)
/* Get Exptime 64 bit register */
#define GET_EXPTIME_LSB_REG (0x7a << MEM_MAP_SHIFT)
#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */
// #define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT)
// #define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */
// #define GET_GATES_LSB_REG (0x7e << MEM_MAP_SHIFT)
// #define GET_GATES_MSB_REG (0x7f << MEM_MAP_SHIFT)
/* Dark Image starting address */
#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)
/* Gain Image starting address */
#define GAIN_IMAGE_REG (0x82 << MEM_MAP_SHIFT)
/* Counter Block Memory starting address */
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)

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slsDetectorServers/gotthardDetectorServer/bin/config_gotthard.txt
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@ -1,23 +0,0 @@
#masterflags (no_master, is_master, is_slave)
masterflags no_master
#master default delay
masterdefaultdelay 70
#patternphase
patternphase 0
#adcphase
adcphase 0
#slave pattern phase
slavepatternphase 0
#slave adc phase
slaveadcphase 0
#rst to sw1 delay
rsttosw1delay 2
#start acquisition delay
startacqdelay 1

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slsDetectorServers/gotthardDetectorServer/config_gotthard.txt
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@ -1,23 +0,0 @@
#masterflags (no_master, is_master, is_slave)
masterflags no_master
#master default delay
masterdefaultdelay 70
#patternphase
patternphase 0
#adcphase
adcphase 0
#slave pattern phase
slavepatternphase 0
#slave adc phase
slaveadcphase 0
#rst to sw1 delay
rsttosw1delay 2
#start acquisition delay
startacqdelay 1

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slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
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159
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
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// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
#include "sls/sls_detector_defs.h"
#include <stdlib.h>
#define NUM_HARDWARE_VERSIONS (2)
#define HARDWARE_VERSION_NUMBERS \
{ 0x1, 0x2 }
#define HARDWARE_VERSION_NAMES \
{ "1.0", "2.0" }
#define LINKED_SERVER_NAME "gotthardDetectorServer"
#ifdef VIRTUAL
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
#else
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
#endif
/* Enums */
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
G_VREF_DS,
G_VCASCN_PB,
G_VCASCP_PB,
G_VOUT_CM,
G_VCASC_OUT,
G_VIN_CM,
G_VREF_COMP,
G_IB_TESTC
};
enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
#define CLK_NAMES "adc"
#define DAC_NAMES \
"vref_ds", "vcascn_pb", "vcascp_pb", "vout_cm", "vcasc_out", "vin_cm", \
"vref_comp", "ib_testc"
#define DEFAULT_DAC_VALS \
{ \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \
1480, /* G_VCASCP_PB */ \
1520, /* G_VOUT_CM */ \
1320, /* G_VCASC_OUT */ \
1350, /* G_VIN_CM */ \
350, /* G_VREF_COMP */ \
2001 /* G_IB_TESTC */ \
};
/* for 25 um */
#define CONFIG_FILE "config_gotthard.txt"
/* Hardware Definitions */
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (8)
#define NCHIPS_PER_ADC (2)
#define NCHAN_PER_ADC (256)
#define DYNAMIC_RANGE (16)
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define CLK_FREQ (32007729) // Hz
#define MAX_EXT_SIGNALS (1)
/** Firmware Definitions */
#define IP_PACKET_SIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define UDP_PACKETSIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
#define DEFAULT_DELAY (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
/** ENEt conf structs */
typedef struct mac_header_struct {
u_int8_t mac_dest_mac2;
u_int8_t mac_dest_mac1;
u_int8_t mac_dummy1;
u_int8_t mac_dummy2;
u_int8_t mac_dest_mac6;
u_int8_t mac_dest_mac5;
u_int8_t mac_dest_mac4;
u_int8_t mac_dest_mac3;
u_int8_t mac_src_mac4;
u_int8_t mac_src_mac3;
u_int8_t mac_src_mac2;
u_int8_t mac_src_mac1;
u_int16_t mac_ether_type;
u_int8_t mac_src_mac6;
u_int8_t mac_src_mac5;
} mac_header;
typedef struct ip_header_struct {
u_int16_t ip_len;
u_int8_t ip_tos;
u_int8_t ip_ihl : 4, ip_ver : 4;
u_int16_t ip_offset : 13, ip_flag : 3;
u_int16_t ip_ident;
u_int16_t ip_chksum;
u_int8_t ip_protocol;
u_int8_t ip_ttl;
u_int32_t ip_sourceip;
u_int32_t ip_destip;
} ip_header;
typedef struct udp_header_struct {
u_int16_t udp_destport;
u_int16_t udp_srcport;
u_int16_t udp_chksum;
u_int16_t udp_len;
} udp_header;
typedef struct mac_conf_struct {
mac_header mac;
ip_header ip;
udp_header udp;
u_int32_t npack;
u_int32_t lpack;
u_int32_t npad;
u_int32_t cdone;
} mac_conf;
typedef struct tse_conf_struct {
u_int32_t rev; // 0x0
u_int32_t scratch;
u_int32_t command_config;
u_int32_t mac_0; // 0x3
u_int32_t mac_1;
u_int32_t frm_length;
u_int32_t pause_quant;
u_int32_t rx_section_empty; // 0x7
u_int32_t rx_section_full;
u_int32_t tx_section_empty;
u_int32_t tx_section_full;
u_int32_t rx_almost_empty; // 0xB
u_int32_t rx_almost_full;
u_int32_t tx_almost_empty;
u_int32_t tx_almost_full;
u_int32_t mdio_addr0; // 0xF
u_int32_t mdio_addr1;
} tse_conf;

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slsDetectorServers/slsDetectorServer/include/AD9252.h
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// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
#include <inttypes.h>
/**
* Set Defines
* @param reg spi register
* @param cmsk chip select mask
* @param clkmsk clock output mask
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI
*/
void AD9252_Disable();
/**
* Set SPI reg value
* @param codata value to be set
*/
void AD9252_Set(int addr, int val);
/**
* Configure
*/
void AD9252_Configure();

79
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
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@ -2,27 +2,17 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "sls/sls_detector_defs.h"
#include "slsDetectorServer_defs.h" // DAC_INDEX, ADC_INDEX, also include RegisterDefs.h
#ifdef GOTTHARDD
#include "AD9252.h" // old board compatibility
#include "clogger.h" // runState(enum TLogLevel)
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD)
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#endif
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "programViaNios.h"
#elif defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(GOTTHARDD)
#include "programViaBlackfin.h"
#endif
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "nios.h"
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD)
#include "programViaNios.h"
#elif defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
#include "blackfin.h"
#include "programViaBlackfin.h"
#endif
#ifdef ARMPROCESSOR
@ -76,8 +66,7 @@ int testBus();
#endif
#endif
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
#if ((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
defined(VIRTUAL))
void setTestImageMode(int ival);
int getTestImageMode();
@ -102,7 +91,7 @@ u_int16_t getHardwareVersionNumber();
u_int16_t getHardwareSerialNumber();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D) || \
defined(MYTHEN3D) || defined(GOTTHARDD)
defined(MYTHEN3D)
int isHardwareVersion_1_0();
#endif
#if defined(JUNGFRAUD)
@ -162,8 +151,7 @@ void setADIFDefaults();
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(JUNGFRAUD)
int readConfigFile();
#endif
#if defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
int checkCommandLineConfiguration();
#endif
#ifdef EIGERD
@ -177,9 +165,6 @@ int readRegister(uint32_t offset, uint32_t *retval);
int setBit(const uint32_t addr, const int nBit, int validate);
int clearBit(const uint32_t addr, const int nBit, int validate);
int getBit(const uint32_t addr, const int nBit, int *retval);
#elif GOTTHARDD
void writeRegister16And32(uint32_t offset, uint32_t data);
uint32_t readRegister16And32(uint32_t offset);
#endif
// firmware functions (resets)
@ -205,26 +190,11 @@ int resetChip(char *mess);
void cleanFifos();
void resetCore();
void resetPeripheral();
#elif GOTTHARDD
void setPhaseShiftOnce();
void setPhaseShift(int numphaseshift);
void cleanFifos();
void setADCSyncRegister();
void setDAQRegister();
void setChipOfInterestRegister(int adc);
void setROIADC(int adc);
void setGbitReadout();
int readConfigFile();
void setMasterSlaveConfiguration();
#endif
// parameters - dr, roi
int setDynamicRange(int dr);
int getDynamicRange(int *retval);
#ifdef GOTTHARDD
int setROI(ROI arg);
ROI getROI();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD)
void setADCInvertRegister(uint32_t val);
uint32_t getADCInvertRegister();
@ -336,9 +306,8 @@ void updatePacketizing();
int64_t getNumFramesLeft();
int64_t getNumTriggersLeft();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARDD) || \
defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
int64_t getDelayAfterTriggerLeft();
@ -347,9 +316,6 @@ int64_t getPeriodLeft();
#ifdef GOTTHARD2D
int64_t getNumBurstsLeft();
#endif
#ifdef GOTTHARDD
int64_t getExpTimeLeft();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
int64_t getFramesFromStart();
@ -462,8 +428,8 @@ int setMaster(enum MASTERINDEX m);
int setTop(enum TOPINDEX t);
int isTop(int *retval);
#endif
#if defined(MYTHEN3D) || defined(EIGERD) || defined(GOTTHARDD) || \
defined(GOTTHARD2D) || defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(MYTHEN3D) || defined(EIGERD) || defined(GOTTHARD2D) || \
defined(JUNGFRAUD) || defined(MOENCHD)
int isMaster(int *retval);
#endif
@ -489,15 +455,12 @@ int setAnalogPulsing(int enable);
int setNegativePolarity(int enable);
int setDACS(int *dacs);
#endif
#if defined(GOTTHARDD) || defined(MYTHEN3D)
#if defined(MYTHEN3D)
void setExtSignal(int signalIndex, enum externalSignalFlag mode);
int getExtSignal(int signalIndex);
#endif
// configure mac
#ifdef GOTTHARDD
void calcChecksum(mac_conf *mac, int sourceip, int destip);
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D)
void setNumberofUDPInterfaces(int val);
#endif
@ -525,9 +488,6 @@ void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip,
defined(XILINX_CHIPTESTBOARDD)
void calcChecksum(udp_header *udp);
#endif
#ifdef GOTTHARDD
int getAdcConfigured();
#endif
int configureMAC();
int setDetectorPosition(int pos[]);
@ -641,10 +601,6 @@ int getActivate(int *retval);
int getDataStream(enum portPosition port, int *retval);
int setDataStream(enum portPosition port, int enable);
// gotthard specific - adc phase
#elif GOTTHARDD
int setPhase(enum CLKINDEX ind, int val, int degrees);
#elif MYTHEN3D
int checkDetectorType(char *mess);
int powerChip(int on);
@ -763,16 +719,11 @@ int checkFifoForEndOfAcquisition();
int readFrameFromFifo();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
u_int32_t runBusy();
#endif
#ifdef GOTTHARDD
u_int32_t runState(enum TLogLevel lev);
#endif
// common
int calculateDataBytes();
int getTotalNumberOfChannels();

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slsDetectorServers/slsDetectorServer/src/AD9252.c
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// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "AD9252.h"
#include "blackfin.h"
#include "clogger.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD9252 ADC DEFINES */
#define AD9252_ADC_NUMBITS (24)
// default value is 0xF
#define AD9252_DEV_IND_2_REG (0x04)
#define AD9252_CHAN_H_OFST (0)
#define AD9252_CHAN_H_MSK (0x00000001 << AD9252_CHAN_H_OFST)
#define AD9252_CHAN_G_OFST (1)
#define AD9252_CHAN_G_MSK (0x00000001 << AD9252_CHAN_G_OFST)
#define AD9252_CHAN_F_OFST (2)
#define AD9252_CHAN_F_MSK (0x00000001 << AD9252_CHAN_F_OFST)
#define AD9252_CHAN_E_OFST (3)
#define AD9252_CHAN_E_MSK (0x00000001 << AD9252_CHAN_E_OFST)
// default value is 0x0F
#define AD9252_DEV_IND_1_REG (0x05)
#define AD9252_CHAN_D_OFST (0)
#define AD9252_CHAN_D_MSK (0x00000001 << AD9252_CHAN_D_OFST)
#define AD9252_CHAN_C_OFST (1)
#define AD9252_CHAN_C_MSK (0x00000001 << AD9252_CHAN_C_OFST)
#define AD9252_CHAN_B_OFST (2)
#define AD9252_CHAN_B_MSK (0x00000001 << AD9252_CHAN_B_OFST)
#define AD9252_CHAN_A_OFST (3)
#define AD9252_CHAN_A_MSK (0x00000001 << AD9252_CHAN_A_OFST)
#define AD9252_CLK_CH_DCO_OFST (4)
#define AD9252_CLK_CH_DCO_MSK (0x00000001 << AD9252_CLK_CH_DCO_OFST)
#define AD9252_CLK_CH_IFCO_OFST (5)
#define AD9252_CLK_CH_IFCO_MSK (0x00000001 << AD9252_CLK_CH_IFCO_OFST)
// default value is 0x00
#define AD9252_POWER_MODE_REG (0x08)
#define AD9252_POWER_INTERNAL_OFST (0)
#define AD9252_POWER_INTERNAL_MSK (0x00000007 << AD9252_POWER_INTERNAL_OFST)
#define AD9252_INT_CHIP_RUN_VAL \
((0x0 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_FULL_PWR_DWN_VAL \
((0x1 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_STANDBY_VAL \
((0x2 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_RESET_VAL \
((0x3 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
// default value is 0x0
#define AD9252_TEST_MODE_REG (0x0D)
#define AD9252_OUT_TEST_OFST (0)
#define AD9252_OUT_TEST_MSK (0x0000000F << AD9252_OUT_TEST_OFST)
#define AD9252_TST_OFF_VAL ((0x0 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MDSCL_SHRT_VAL \
((0x1 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PSTV_FS_VAL \
((0x2 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_NGTV_FS_VAL \
((0x3 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_ALTRNTNG_CHKRBRD_VAL \
((0x4 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_23_SQNC_VAL \
((0x5 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_9_SQNC__VAL \
((0x6 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_WRD_TGGL_VAL \
((0x7 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_USR_INPT_VAL \
((0x8 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_BT_TGGL_VAL \
((0x9 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_x_SYNC_VAL \
((0xa << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_BIT_HGH_VAL \
((0xb << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MXD_BT_FRQ_VAL \
((0xc << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_RST_SHRT_GN_OFST (4)
#define AD9252_TST_RST_SHRT_GN_MSK (0x00000001 << AD9252_TST_RST_SHRT_GN_OFST)
#define AD9252_TST_RST_LNG_GN_OFST (5)
#define AD9252_TST_RST_LNG_GN_MSK (0x00000001 << AD9252_TST_RST_LNG_GN_OFST)
#define AD9252_USER_IN_MODE_OFST (6)
#define AD9252_USER_IN_MODE_MSK (0x00000003 << AD9252_USER_IN_MODE_OFST)
#define AD9252_USR_IN_SNGL_VAL \
((0x0 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_VAL \
((0x1 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_ONC_VAL \
((0x2 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_ONC_VAL \
((0x3 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
// default value is 0x00
#define AD9252_OUT_MODE_REG (0x14)
#define AD9252_OUT_FORMAT_OFST (0)
#define AD9252_OUT_FORMAT_MSK (0x00000003 << AD9252_OUT_FORMAT_OFST)
#define AD9252_OUT_BINARY_OFST_VAL \
((0x0 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_TWOS_COMPL_VAL \
((0x1 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_OTPT_INVRT_OFST (2)
#define AD9252_OUT_OTPT_INVRT_MSK (0x00000001 << AD9252_OUT_OTPT_INVRT_OFST)
#define AD9252_OUT_LVDS_OPT_OFST (6)
#define AD9252_OUT_LVDS_OPT_MSK (0x00000001 << AD9252_OUT_LVDS_OPT_OFST)
#define AD9252_OUT_LVDS_ANSI_VAL \
((0x0 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_IEEE_VAL \
((0x1 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
// default value is 0x3
#define AD9252_OUT_PHASE_REG (0x16)
#define AD9252_OUT_CLK_OFST (0)
#define AD9252_OUT_CLK_MSK (0x0000000F << AD9252_OUT_CLK_OFST)
#define AD9252_OUT_CLK_0_VAL ((0x0 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_60_VAL \
((0x1 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_120_VAL \
((0x2 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_180_VAL \
((0x3 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_300_VAL \
((0x5 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_360_VAL \
((0x6 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_480_VAL \
((0x8 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_540_VAL \
((0x9 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_600_VAL \
((0xa << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_660_VAL \
((0xb << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK) // 0xb - 0xf is 660
// defines from the fpga
uint32_t AD9252_Reg = 0x0;
uint32_t AD9252_CsMask = 0x0;
uint32_t AD9252_ClkMask = 0x0;
uint32_t AD9252_DigMask = 0x0;
int AD9252_DigOffset = 0x0;
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst) {
AD9252_Reg = reg;
AD9252_CsMask = cmsk;
AD9252_ClkMask = clkmsk;
AD9252_DigMask = dmsk;
AD9252_DigOffset = dofst;
}
void AD9252_Disable() {
bus_w(AD9252_Reg, (bus_r(AD9252_Reg) | AD9252_CsMask | AD9252_ClkMask) &
~(AD9252_DigMask));
}
void AD9252_Set(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO,
("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9252_Reg, codata, AD9252_CsMask, AD9252_ADC_NUMBITS,
AD9252_ClkMask, AD9252_DigMask, AD9252_DigOffset, 0);
}
void AD9252_Configure() {
LOG(logINFOBLUE, ("Configuring ADC9252:\n"));
// power mode reset
LOG(logINFO, ("\tPower mode reset\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_RESET_VAL);
// power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_CHIP_RUN_VAL);
// binary offset
LOG(logINFO, ("\tBinary offset\n"));
AD9252_Set(AD9252_OUT_MODE_REG, AD9252_OUT_BINARY_OFST_VAL);
// output clock phase
#ifdef GOTTHARDD
LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
#else
LOG(logINFO, ("\tOutput clock phase: 60\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_60_VAL);
#endif
// lvds-iee reduced , binary offset
LOG(logINFO, ("\tLvds-iee reduced, binary offset\n"));
AD9252_Set(AD9252_OUT_MODE_REG, AD9252_OUT_LVDS_IEEE_VAL);
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9252_Set(AD9252_DEV_IND_2_REG, AD9252_CHAN_H_MSK | AD9252_CHAN_G_MSK |
AD9252_CHAN_F_MSK | AD9252_CHAN_E_MSK);
AD9252_Set(AD9252_DEV_IND_1_REG, AD9252_CHAN_D_MSK | AD9252_CHAN_C_MSK |
AD9252_CHAN_B_MSK | AD9252_CHAN_A_MSK |
AD9252_CLK_CH_DCO_MSK |
AD9252_CLK_CH_IFCO_MSK);
// no test mode
LOG(logINFO, ("\tNo test mode\n"));
AD9252_Set(AD9252_TEST_MODE_REG, AD9252_TST_OFF_VAL);
#ifdef TESTADC
LOG(logINFOBLUE, ("Putting ADC in Test Mode!\n");
// mixed bit frequency test mode
LOG(logINFO, ("\tMixed bit frequency test mode\n"));
AD9252_Set(AD9252_TEST_MODE_REG, AD9252_TST_MXD_BT_FRQ_VAL);
#endif
}

2
slsDetectorServers/slsDetectorServer/src/AD9257.c
View File

@ -318,7 +318,7 @@ void AD9257_Configure() {
AD9257_CLK_CH_IFCO_MSK);
// vref
#if defined(GOTTHARDD) || defined(MOENCHD)
#if defined(MOENCHD)
LOG(logINFO, ("\tVref default at 2.0\n"));
AD9257_SetVrefVoltage(AD9257_VREF_DEFAULT_VAL, 0);
#else

3
slsDetectorServers/slsDetectorServer/src/common.c
View File

@ -504,8 +504,7 @@ int setupDetectorServer(char *mess, char *sname) {
// blackfin boards (respawn) (only kept for backwards compatibility)
#ifndef VIRTUAL
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(GOTTHARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD)
// delete every line with DetectorServer in /etc/inittab
strcpy(cmd, "sed -i '/DetectorServer/d' /etc/inittab");
if (executeCommand(cmd, retvals, logDEBUG1) == FAIL) {

42
slsDetectorServers/slsDetectorServer/src/slsDetectorServer.c
View File

@ -30,11 +30,7 @@ extern int checkModuleFlag;
extern int ignoreConfigFileFlag;
// Global variables from slsDetectorFunctionList
#ifdef GOTTHARDD
extern int phaseShift;
#endif
#if defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
extern int masterCommandLine;
#endif
#ifdef EIGERD
@ -59,8 +55,7 @@ int main(int argc, char *argv[]) {
char version[MAX_STR_LENGTH] = {0};
memset(version, 0, MAX_STR_LENGTH);
ignoreConfigFileFlag = 0;
#if defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
masterCommandLine = -1;
#endif
#ifdef EIGERD
@ -82,17 +77,16 @@ int main(int argc, char *argv[]) {
"\t-g, --nomodule : [Mythen3][Gotthard2][Xilinx Ctb] \n"
"\t Generic or No Module mode. Skips "
"detector type checks. \n"
"\t-f, --phaseshift <value> : [Gotthard] only. Sets phase shift. \n"
"\t-d, --devel : Developer mode. Skips firmware "
"checks. \n"
"\t-u, --update : Update mode. Skips firmware checks "
"and "
"initial detector setup. \n"
"\t-i, --ignore-config : "
"[Eiger][Jungfrau][Gotthard][Gotthard2] \n"
"[Eiger][Jungfrau][Gotthard2] \n"
"\t Ignore config file. \n"
"\t-m, --master <master> : "
"[Eiger][Mythen3][Gotthard][Gotthard2] \n"
"[Eiger][Mythen3][Gotthard2] \n"
"\t Set Master to 0 or 1. Precedence "
"over "
"config file. Only for virtual servers except Eiger. \n"
@ -117,7 +111,6 @@ int main(int argc, char *argv[]) {
{"help", no_argument, NULL, 'h'},
{"version", no_argument, NULL, 'v'},
{"port", required_argument, NULL, 'p'},
{"phaseshift", required_argument, NULL, 'f'},
{"nomodule", no_argument, NULL, 'g'}, // generic
{"devel", no_argument, NULL, 'd'},
{"update", no_argument, NULL, 'u'},
@ -133,7 +126,7 @@ int main(int argc, char *argv[]) {
int c = 0;
while (c != -1) {
c = getopt_long(argc, argv, "hvp:f:gduim:t:s", long_options,
c = getopt_long(argc, argv, "hvp:gduim:t:s", long_options,
&option_index);
// Detect the end of the options
@ -143,9 +136,7 @@ int main(int argc, char *argv[]) {
switch (c) {
case 'v':
#ifdef GOTTHARDD
strcpy(version, APIGOTTHARD);
#elif EIGERD
#ifdef EIGERD
strcpy(version, APIEIGER);
#elif JUNGFRAUD
strcpy(version, APIJUNGFRAU);
@ -169,21 +160,6 @@ int main(int argc, char *argv[]) {
LOG(logINFO, ("Detected port: %d\n", portno));
break;
case 'f':
#ifndef GOTTHARDD
LOG(logERROR,
("Phase shift argument not implemented for this detector\n"));
exit(EXIT_FAILURE);
#else
if (sscanf(optarg, "%d", &phaseShift) != 1) {
LOG(logERROR,
("Cannot scan phase shift argument\n%s", helpMessage));
exit(EXIT_FAILURE);
}
LOG(logINFO, ("Detected phase shift: %d\n", phaseShift));
#endif
break;
case 'g':
LOG(logINFO, ("Detected generic mode (no module)\n"));
checkModuleFlag = 0;
@ -205,8 +181,7 @@ int main(int argc, char *argv[]) {
break;
case 'i':
#if defined(EIGERD) || defined(GOTTHARDD) || defined(GOTTHARD2D) || \
defined(JUNGFRAUD)
#if defined(EIGERD) || defined(GOTTHARD2D) || defined(JUNGFRAUD)
LOG(logINFO, ("Ignoring config file\n"));
ignoreConfigFileFlag = 1;
#else
@ -220,8 +195,7 @@ int main(int argc, char *argv[]) {
LOG(logERROR, ("Cannot set master via the detector server for this "
"detector\n"));
exit(EXIT_FAILURE);
#elif defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#elif defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
if (sscanf(optarg, "%d", &masterCommandLine) != 1) {
LOG(logERROR, ("Cannot scan master argument\n%s", helpMessage));
exit(EXIT_FAILURE);

282
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
View File

@ -20,9 +20,7 @@
#include <unistd.h>
// defined in the detector specific Makefile
#ifdef GOTTHARDD
const enum detectorType myDetectorType = GOTTHARD;
#elif EIGERD
#ifdef EIGERD
const enum detectorType myDetectorType = EIGER;
#elif JUNGFRAUD
const enum detectorType myDetectorType = JUNGFRAU;
@ -281,7 +279,6 @@ void function_table() {
flist[F_SET_STORAGE_CELL_DELAY] = &set_storage_cell_delay;
flist[F_GET_FRAMES_LEFT] = &get_frames_left;
flist[F_GET_TRIGGERS_LEFT] = &get_triggers_left;
flist[F_GET_EXPTIME_LEFT] = &get_exptime_left;
flist[F_GET_PERIOD_LEFT] = &get_period_left;
flist[F_GET_DELAY_AFTER_TRIGGER_LEFT] = &get_delay_after_trigger_left;
flist[F_GET_MEASURED_PERIOD] = &get_measured_period;
@ -290,8 +287,6 @@ void function_table() {
flist[F_GET_ACTUAL_TIME] = &get_actual_time;
flist[F_GET_MEASUREMENT_TIME] = &get_measurement_time;
flist[F_SET_DYNAMIC_RANGE] = &set_dynamic_range;
flist[F_SET_ROI] = &set_roi;
flist[F_GET_ROI] = &get_roi;
flist[F_LOCK_SERVER] = &lock_server;
flist[F_GET_LAST_CLIENT_IP] = &get_last_client_ip;
flist[F_ENABLE_TEN_GIGA] = &enable_ten_giga;
@ -643,7 +638,7 @@ int get_external_signal_flag(int file_des) {
LOG(logDEBUG1, ("Getting external signal flag (%d)\n", arg));
#if !defined(GOTTHARDD) && !defined(MYTHEN3D)
#if !defined(MYTHEN3D)
functionNotImplemented();
#else
// get
@ -674,7 +669,7 @@ int set_external_signal_flag(int file_des) {
LOG(logDEBUG1,
("Setting external signal flag [%d] to %d\n", signalIndex, flag));
#if !defined(GOTTHARDD) && !defined(MYTHEN3D)
#if !defined(MYTHEN3D)
functionNotImplemented();
#else
if (Server_VerifyLock() == OK) {
@ -832,8 +827,8 @@ int set_firmware_test(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Executing firmware test\n"));
#if !defined(GOTTHARDD) && !defined(JUNGFRAUD) && !defined(MOENCHD) && \
!defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(GOTTHARD2D) && !defined(MYTHEN3D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -851,8 +846,8 @@ int set_bus_test(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Executing bus test\n"));
#if !defined(GOTTHARDD) && !defined(JUNGFRAUD) && !defined(MOENCHD) && \
!defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
ret = testBus();
@ -873,8 +868,7 @@ int set_image_test_mode(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Setting image test mode to \n", arg));
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
#if ((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
defined(VIRTUAL))
setTestImageMode(arg);
#else
@ -889,8 +883,7 @@ int get_image_test_mode(int file_des) {
int retval = -1;
LOG(logDEBUG1, ("Getting image test mode\n"));
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
#if ((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
defined(VIRTUAL))
retval = getTestImageMode();
LOG(logDEBUG1, ("image test mode retval: %d\n", retval));
@ -904,32 +897,7 @@ enum DACINDEX getDACIndex(enum dacIndex ind) {
enum DACINDEX serverDacIndex = -1;
// check if dac exists for this detector
switch (ind) {
#ifdef GOTTHARDD
case VREF_DS:
serverDacIndex = G_VREF_DS;
break;
case VCASCN_PB:
serverDacIndex = G_VCASCN_PB;
break;
case VCASCP_PB:
serverDacIndex = G_VCASCP_PB;
break;
case VOUT_CM:
serverDacIndex = G_VOUT_CM;
break;
case VCASC_OUT:
serverDacIndex = G_VCASC_OUT;
break;
case VIN_CM:
serverDacIndex = G_VIN_CM;
break;
case VREF_COMP:
serverDacIndex = G_VREF_COMP;
break;
case IB_TESTC:
serverDacIndex = G_IB_TESTC;
break;
#elif EIGERD
#ifdef EIGERD
case VTHRESHOLD:
serverDacIndex = E_VTHRESHOLD;
break;
@ -1274,15 +1242,7 @@ int validateAndSetDac(enum dacIndex ind, int val, int mV) {
#endif
#endif
#ifdef GOTTHARDD
if (retval == -1) {
ret = FAIL;
strcpy(mess, "Invalid Voltage. Valid values are 0, 90, "
"110, 120, 150, 180, 200\n");
LOG(logERROR, (mess));
} else
validate(&ret, mess, val, retval, "set high voltage", DEC);
#elif EIGERD
#ifdef EIGERD
if ((retval != SLAVE_HIGH_VOLTAGE_READ_VAL) && (retval < 0)) {
ret = FAIL;
if (retval == -1)
@ -1525,7 +1485,7 @@ int get_adc(int file_des) {
serverAdcIndex = TEMP_FPGA;
break;
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD) || defined(MOENCHD)
case TEMPERATURE_FPGA:
serverAdcIndex = TEMP_FPGA;
break;
@ -1694,14 +1654,9 @@ int write_register(int file_des) {
sprintf(mess, "Could not write to register 0x%x.\n", addr);
LOG(logERROR, (mess));
}
#else
#ifdef GOTTHARDD
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr);
#else
writeRegister(addr, val);
uint32_t retval = readRegister(addr);
#endif
LOG(logDEBUG1, ("Write register retval (0x%x): 0x%x\n", addr, retval));
// validate
if (validate && ret == OK && retval != val) {
@ -1738,8 +1693,6 @@ int read_register(int file_des) {
addr);
LOG(logERROR, (mess));
}
#elif GOTTHARDD
retval = readRegister16And32(addr);
#else
retval = readRegister(addr);
#endif
@ -1873,12 +1826,6 @@ void validate_settings(enum detectorSettings sett) {
#elif JUNGFRAUD
case GAIN0:
case HIGHGAIN0:
#elif GOTTHARDD
case DYNAMICGAIN:
case HIGHGAIN:
case LOWGAIN:
case MEDIUMGAIN:
case VERYHIGHGAIN:
#elif GOTTHARD2D
case DYNAMICGAIN:
case FIXGAIN1:
@ -1939,16 +1886,6 @@ int set_settings(int file_des) {
if ((int)isett != GET_FLAG) {
validate(&ret, mess, (int)isett, (int)retval, "set settings", DEC);
#ifdef GOTTHARDD
if (ret == OK) {
ret = resetToDefaultDacs(0);
if (ret == FAIL) {
strcpy(mess, "Could change settings, but could not set to "
"default dacs\n");
LOG(logERROR, (mess));
}
}
#endif
#ifdef MYTHEN3D
// changed for setsettings (direct),
// custom trimbit file (setmodule with myMod.reg as -1),
@ -2707,8 +2644,8 @@ int get_delay_after_trigger(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -2730,8 +2667,8 @@ int set_delay_after_trigger(int file_des) {
LOG(logDEBUG1,
("Setting delay after trigger %lld ns\n", (long long int)arg));
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -2941,8 +2878,8 @@ int get_frames_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -2959,8 +2896,8 @@ int get_triggers_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -2971,28 +2908,13 @@ int get_triggers_left(int file_des) {
return Server_SendResult(file_des, INT64, &retval, sizeof(retval));
}
int get_exptime_left(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#ifndef GOTTHARDD
functionNotImplemented();
#else
// get only
retval = getExpTimeLeft();
LOG(logDEBUG1, ("retval exptime left %lld ns\n", (long long int)retval));
#endif
return Server_SendResult(file_des, INT64, &retval, sizeof(retval));
}
int get_period_left(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -3008,8 +2930,8 @@ int get_delay_after_trigger_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@ -3133,9 +3055,8 @@ int set_dynamic_range(int file_des) {
case 16:
case 32:
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
case 16:
#endif
if (dr >= 0) {
@ -3166,67 +3087,6 @@ int set_dynamic_range(int file_des) {
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}
int set_roi(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
ROI arg;
// receive ROI
if (receiveData(file_des, &arg.xmin, sizeof(int), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &arg.xmax, sizeof(int), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &arg.ymin, sizeof(int), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &arg.ymax, sizeof(int), INT32) < 0)
return printSocketReadError();
LOG(logDEBUG1, ("Set ROI: [%d, %d, %d, %d]\n", arg.xmin, arg.xmax, arg.ymin,
arg.ymax));
#ifndef GOTTHARDD
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
ret = setROI(arg);
if (ret == FAIL) {
sprintf(mess, "Could not set ROI. Invalid xmin or xmax\n");
LOG(logERROR, (mess));
}
// old firmware requires a redo configure mac
else {
configure_mac();
}
}
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int get_roi(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
ROI retval;
#ifndef GOTTHARDD
functionNotImplemented();
#else
// only get
retval = getROI();
LOG(logDEBUG1, ("nRois: (%d, %d, %d, %d)\n", retval.xmin, retval.xmax,
retval.ymin, retval.ymax));
#endif
Server_SendResult(file_des, INT32, NULL, 0);
if (ret != FAIL) {
sendData(file_des, &retval.xmin, sizeof(int), INT32);
sendData(file_des, &retval.xmax, sizeof(int), INT32);
sendData(file_des, &retval.ymin, sizeof(int), INT32);
sendData(file_des, &retval.ymax, sizeof(int), INT32);
}
return ret;
}
int lock_server(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
@ -3276,8 +3136,8 @@ int enable_ten_giga(int file_des) {
return printSocketReadError();
LOG(logDEBUG, ("Setting 10GbE: %d\n", arg));
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARDD) || \
defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
// set & get
@ -3696,12 +3556,6 @@ int write_adc_register(int file_des) {
if (Server_VerifyLock() == OK) {
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD)
AD9257_Set(addr, val);
#elif GOTTHARDD
if (isHardwareVersion_1_0()) {
AD9252_Set(addr, val);
} else {
AD9257_Set(addr, val);
}
#endif
}
#endif
@ -4068,7 +3922,7 @@ int program_fpga(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
#if defined(EIGERD) || defined(GOTTHARDD)
#if defined(EIGERD)
functionNotImplemented();
return Server_SendResult(file_des, INT32, NULL, 0);
#else
@ -4082,8 +3936,7 @@ int reset_fpga(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Reset FPGA\n"));
#if defined(EIGERD) || defined(GOTTHARDD) || defined(GOTTHARD2D) || \
defined(MYTHEN3D)
#if defined(EIGERD) || defined(GOTTHARD2D) || defined(MYTHEN3D)
functionNotImplemented();
#else
// only set
@ -6060,7 +5913,7 @@ int set_clock_phase(int file_des) {
(args[2] == 0 ? "" : "degrees")));
#if !defined(CHIPTESTBOARDD) && !defined(JUNGFRAUD) && !defined(MOENCHD) && \
!defined(GOTTHARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D)
!defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
// only set
@ -6070,8 +5923,7 @@ int set_clock_phase(int file_des) {
int inDegrees = args[2] == 0 ? 0 : 1;
enum CLKINDEX c = 0;
switch (ind) {
#if defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(GOTTHARDD)
#if defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
case ADC_CLOCK:
c = ADC_CLK;
break;
@ -6101,15 +5953,6 @@ int set_clock_phase(int file_des) {
sprintf(modeName, "%s clock (%d) phase %s", clock_names[c], (int)c,
(inDegrees == 0 ? "" : "(degrees)"));
// gotthard1d doesnt take degrees and cannot get phase
#ifdef GOTTHARDD
if (inDegrees != 0) {
ret = FAIL;
strcpy(mess,
"Cannot set phase in degrees for this detector.\n");
LOG(logERROR, (mess));
}
#else
if (getPhase(c, inDegrees) == val) {
LOG(logINFO, ("Same %s: %d\n", modeName, val));
} else if (inDegrees && (val < 0 || val > 359)) {
@ -6126,18 +5969,12 @@ int set_clock_phase(int file_des) {
"phase shifts)\n",
modeName, val, getMaxPhase(c) - 1);
LOG(logERROR, (mess));
}
#endif
else {
} else {
int ret = setPhase(c, val, inDegrees);
if (ret == FAIL) {
sprintf(mess, "Could not set %s to %d.\n", modeName, val);
LOG(logERROR, (mess));
}
// gotthard1d doesnt take degrees and cannot get phase
#ifndef GOTTHARDD
else {
} else {
int retval = getPhase(c, inDegrees);
LOG(logDEBUG1, ("retval %s : %d\n", modeName, retval));
if (!inDegrees) {
@ -6153,7 +5990,6 @@ int set_clock_phase(int file_des) {
}
}
}
#endif
}
}
}
@ -7471,32 +7307,7 @@ int get_receiver_parameters(int file_des) {
if (n < 0)
return printSocketReadError();
// roi
{
ROI roi;
#ifdef GOTTHARDD
roi = getROI();
#else
roi.xmin = -1;
roi.xmax = -1;
roi.ymin = -1;
roi.ymax = -1;
#endif
n += sendData(file_des, &roi.xmin, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
n += sendData(file_des, &roi.xmax, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
n += sendData(file_des, &roi.ymin, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
n += sendData(file_des, &roi.ymax, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
}
// counter mask
// counter mask
#ifdef MYTHEN3D
u32 = getCounterMask();
#else
@ -8601,8 +8412,8 @@ int get_master(int file_des) {
LOG(logDEBUG1, ("Getting master\n"));
#if !defined(MYTHEN3D) && !defined(EIGERD) && !defined(GOTTHARDD) && \
!defined(GOTTHARD2D) && !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(MYTHEN3D) && !defined(EIGERD) && !defined(GOTTHARD2D) && \
!defined(JUNGFRAUD) && !defined(MOENCHD)
functionNotImplemented();
#else
ret = isMaster(&retval);
@ -9897,8 +9708,7 @@ void receive_program_via_blackfin(int file_des, enum PROGRAM_INDEX index,
char *checksum, char *serverName,
int forceDeleteNormalFile) {
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(GOTTHARDD)
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD)
ret = FAIL;
sprintf(mess,
"Could not %s. program via blackfin not implmented for this "
@ -10605,15 +10415,9 @@ int set_bit(int file_des) {
ret = setBit(addr, nBit, validate);
#else
uint32_t bitmask = (1 << nBit);
#ifdef GOTTHARDD
uint32_t val = readRegister16And32(addr) | bitmask;
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr) | bitmask;
#else
uint32_t val = readRegister(addr) | bitmask;
writeRegister(addr, val);
uint32_t retval = readRegister(addr) | bitmask;
#endif
if (validate && (!(retval & bitmask))) {
ret = FAIL;
}
@ -10654,15 +10458,9 @@ int clear_bit(int file_des) {
ret = clearBit(addr, nBit, validate);
#else
uint32_t bitmask = (1 << nBit);
#ifdef GOTTHARDD
uint32_t val = readRegister16And32(addr) & ~bitmask;
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr) & ~bitmask;
#else
uint32_t val = readRegister(addr) & ~bitmask;
writeRegister(addr, val);
uint32_t retval = readRegister(addr) & ~bitmask;
#endif
if (validate && (retval & bitmask)) {
ret = FAIL;
}
@ -10702,12 +10500,8 @@ int get_bit(int file_des) {
sprintf(mess, "Could not get bit %d.\n", nBit);
LOG(logERROR, (mess));
}
#else
#ifdef GOTTHARDD
uint32_t regval = readRegister16And32(addr);
#else
uint32_t regval = readRegister(addr);
#endif
retval = (regval & (1 << nBit)) >> nBit;
LOG(logDEBUG1, ("regval: 0x%x bit value:0%d\n", regval, retval));
#endif

BIN
slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer
View File

Binary file not shown.

3
slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c
View File

@ -492,6 +492,9 @@ void setTransceiverAlignment(int align) {
#endif
int isTransceiverAligned() {
#ifdef VIRTUAL
return 1;
#endif
int times = 0;
int retval = bus_r(TRANSCEIVERSTATUS2) & RXLOCKED_MSK;
while (retval) {