mythen3, gotthard2: bug fix- changing wrong pll phases when changing frequency

This commit is contained in:
maliakal_d 2020-07-13 15:47:43 +02:00
parent bef35eb3d6
commit 293fda0c7a
5 changed files with 5 additions and 5 deletions

View File

@ -1710,7 +1710,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
} }
// phase is reset by pll (when setting output frequency) // phase is reset by pll (when setting output frequency)
if (ind >= READOUT_C0) { if (ind < SYSTEM_C0) {
clkPhase[READOUT_C0] = 0; clkPhase[READOUT_C0] = 0;
clkPhase[READOUT_C1] = 0; clkPhase[READOUT_C1] = 0;
} else { } else {
@ -2500,4 +2500,4 @@ int getTotalNumberOfChannels() {
} }
int getNumberOfChips() { return NCHIP; } int getNumberOfChips() { return NCHIP; }
int getNumberOfDACs() { return NDAC; } int getNumberOfDACs() { return NDAC; }
int getNumberOfChannelsPerChip() { return NCHAN; } int getNumberOfChannelsPerChip() { return NCHAN; }

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@ -1929,7 +1929,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
clkDivider[ind])); clkDivider[ind]));
// phase is reset by pll (when setting output frequency) // phase is reset by pll (when setting output frequency)
if (ind >= READOUT_C0) { if (ind < SYSTEM_C0) {
clkPhase[READOUT_C0] = 0; clkPhase[READOUT_C0] = 0;
clkPhase[READOUT_C1] = 0; clkPhase[READOUT_C1] = 0;
} else { } else {

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@ -5,8 +5,8 @@
#define APIGUI 0x200409 #define APIGUI 0x200409
#define APICTB 0x200703 #define APICTB 0x200703
#define APIGOTTHARD 0x200703 #define APIGOTTHARD 0x200703
#define APIGOTTHARD2 0x200703
#define APIJUNGFRAU 0x200703 #define APIJUNGFRAU 0x200703
#define APIMOENCH 0x200702 #define APIMOENCH 0x200702
#define APIEIGER 0x200703 #define APIEIGER 0x200703
#define APIMYTHEN3 0x200708 #define APIGOTTHARD2 0x200713
#define APIMYTHEN3 0x200713