filter cell (only chipv1.1)

This commit is contained in:
2021-08-06 14:42:41 +02:00
parent 0a58f13fe1
commit 2934ccbf2c
13 changed files with 147 additions and 10 deletions

View File

@ -475,7 +475,10 @@ void setupDetector() {
setThresholdTemperature(DEFAULT_TMP_THRSHLD);
setTemperatureEvent(0);
setFlipRows(DEFAULT_FLIP_ROWS);
setFilterResistor(DEFAULT_FILTER_RESISTOR);
if (getChipVersion() == 11) {
setFilterResistor(DEFAULT_FILTER_RESISTOR);
setFilterCell(DEFAULT_FILTER_CELL);
}
}
int resetToDefaultDacs(int hardReset) {
@ -2055,6 +2058,32 @@ int setFilterResistor(int value) {
return FAIL;
}
int getFilterCell() {
#ifdef VIRTUAL
uint32_t addr = CONFIG_V11_REG;
#else
uint32_t addr = CONFIG_V11_STATUS_REG;
#endif
uint32_t value = (bus_r(addr) & CONFIG_V11_FLTR_CLL_MSK) >> CONFIG_V11_FLTR_CLL_OFST;
// count number of bits = which icell
return (__builtin_popcount(value));
}
void setFilterCell(int iCell) {
uint32_t value = 0;
// sets the corresponding cell and the cells before it
if (iCell != 0) {
value = iCell;
if (value > 1) {
value += (value - 1);
}
}
uint32_t addr = CONFIG_V11_REG;
bus_w(addr, bus_r(addr) &~ CONFIG_V11_FLTR_CLL_MSK);
bus_w(addr, bus_r(addr) | ((value << CONFIG_V11_FLTR_CLL_OFST) & CONFIG_V11_FLTR_CLL_MSK));
LOG(logINFO, ("Setting Filter Cell to %d [Reg:0x%x]\n", iCell, bus_r(addr)));
}
int getTenGigaFlowControl() {
return ((bus_r(CONFIG_REG) & CONFIG_ETHRNT_FLW_CNTRL_MSK) >>
CONFIG_ETHRNT_FLW_CNTRL_OFST);

View File

@ -107,11 +107,13 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define DEFAULT_STRG_CLL_DLY (0)
#define DEFAULT_FLIP_ROWS (0)
#define DEFAULT_FILTER_RESISTOR (1) // higher resistor
#define DEFAULT_FILTER_CELL (0)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define MAX_FILTER_CELL_VAL (12)
/* Defines in the Firmware */
#define MAX_TIMESLOT_VAL (0x1F)