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dev:removed storage cells for moench (#603)

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* removed storage cells for moench
* rxr: also setting moench like jungfrau in implementation of ports
This commit is contained in:
Dhanya Thattil
2023-02-24 10:00:31 +01:00
committed by GitHub
parent eb025b54ef
commit 276dc52196
14 changed files with 134 additions and 292 deletions
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25
slsDetectorServers/moenchDetectorServer/RegisterDefs.h
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@ -104,8 +104,6 @@
#define CONFIG_V11_STATUS_FLTR_CLL_OFST (0)
#define CONFIG_V11_STATUS_FLTR_CLL_MSK (0x00000FFF << CONFIG_V11_STATUS_FLTR_CLL_OFST)
#define CONFIG_V11_STATUS_STRG_CLL_OFST (12)
#define CONFIG_V11_STATUS_STRG_CLL_MSK (0x0000000F << CONFIG_V11_STATUS_STRG_CLL_OFST)
// CSM mode = high current (100%), low current (16%)
#define CONFIG_V11_STATUS_CRRNT_SRC_LOW_OFST (19)
#define CONFIG_V11_STATUS_CRRNT_SRC_LOW_MSK (0x00000001 << CONFIG_V11_STATUS_CRRNT_SRC_LOW_OFST)
@ -231,8 +229,6 @@
#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
#define CONTROL_MASTER_OFST (15)
#define CONTROL_MASTER_MSK (0x00000001 << CONTROL_MASTER_OFST)
#define CONTROL_STORAGE_CELL_NUM_OFST (16)
#define CONTROL_STORAGE_CELL_NUM_MSK (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST (20)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK (0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ENDPTS_START_OFST (26)
@ -260,8 +256,6 @@
#define CONFIG_V11_FLTR_CLL_OFST (0)
#define CONFIG_V11_FLTR_CLL_MSK (0x00000FFF << CONFIG_V11_FLTR_CLL_OFST)
#define CONFIG_V11_STRG_CLL_OFST (12)
#define CONFIG_V11_STRG_CLL_MSK (0x0000000F << CONFIG_V11_STRG_CLL_OFST)
// CSM mode = high current (100%), low current (16%)
#define CONFIG_V11_CRRNT_SRC_LOW_OFST (19)
#define CONFIG_V11_CRRNT_SRC_LOW_MSK (0x00000001 << CONFIG_V11_CRRNT_SRC_LOW_OFST)
@ -352,8 +346,6 @@
#define DAQ_CMP_RST_MSK (0x00000001 << DAQ_CMP_RST_OFST)
#define DAQ_CHIP11_VRSN_OFST (7)
#define DAQ_CHIP11_VRSN_MSK (0x00000001 << DAQ_CHIP11_VRSN_OFST)
#define DAQ_STRG_CELL_SLCT_OFST (8)
#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
#define DAQ_FRCE_SWTCH_GAIN_MSK (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
#define DAQ_FRCE_GAIN_STG_0_VAL ((0x0 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
@ -445,23 +437,6 @@ Time before end of exposure when comparator is disabled */
#define MOD_ID_OFST (0)
#define MOD_ID_MSK (0x0000FFFF << MOD_ID_OFST)
/* ASIC Control Register */
#define ASIC_CTRL_REG (0x7F << MEM_MAP_SHIFT)
// tPC = (PCT + 1) * 25ns
#define ASIC_CTRL_PRCHRG_TMR_OFST (0)
#define ASIC_CTRL_PRCHRG_TMR_MSK (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
#define ASIC_CTRL_PRCHRG_TMR_VAL ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
// tDS = (DST + 1) * 25ns
#define ASIC_CTRL_DS_TMR_OFST (8)
#define ASIC_CTRL_DS_TMR_MSK (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
#define ASIC_CTRL_DS_TMR_VAL ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
#define ASIC_CTRL_DS_TMR_CHIP1_1_VAL ((0xFF << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage
// cells)
#define ASIC_CTRL_EXPSRE_TMR_OFST (16)
#define ASIC_CTRL_EXPSRE_TMR_MSK (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
#define ASIC_CTRL_EXPSRE_TMR_MAX_VAL (0x0000FFFF / (CLK_RUN * 1E-3))
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */

BIN
slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
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127
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -518,7 +518,7 @@ void setupDetector() {
resetCore();
alignDeserializer();
// configureASICTimer(); ASIC_CTRL_REG to be removed along with storage cell
// delay
bus_w(ADC_PORT_INVERT_REG,
(isHardwareVersion_1_0() ? ADC_PORT_INVERT_BOARD2_VAL
@ -536,14 +536,6 @@ void setupDetector() {
setExpTime(DEFAULT_EXPTIME);
setPeriod(DEFAULT_PERIOD);
setDelayAfterTrigger(DEFAULT_DELAY);
if (getChipVersion() == 11) {
selectStoragecellStart(DEFAULT_STRG_CLL_STRT_CHIP11);
} else {
setNumAdditionalStorageCells(DEFAULT_NUM_STRG_CLLS);
selectStoragecellStart(DEFAULT_STRG_CLL_STRT);
// not applicable for chipv1.1
setStorageCellDelay(DEFAULT_STRG_CLL_DLY);
}
setTiming(DEFAULT_TIMING_MODE);
setNextFrameNumber(DEFAULT_STARTING_FRAME_NUMBER);
@ -891,66 +883,6 @@ uint32_t getADCInvertRegister() {
}
/* parameters - timer */
int selectStoragecellStart(int pos) {
int value = pos;
uint32_t addr = DAQ_REG;
uint32_t mask = DAQ_STRG_CELL_SLCT_MSK;
int offset = DAQ_STRG_CELL_SLCT_OFST;
if (getChipVersion() == 11) {
// set the bit
value = 1 << pos;
addr = CONFIG_V11_REG;
mask = CONFIG_V11_STRG_CLL_MSK;
offset = CONFIG_V11_STRG_CLL_OFST;
}
if (pos >= 0) {
LOG(logINFO, ("Setting storage cell start: %d\n", pos));
bus_w(addr, bus_r(addr) & ~mask);
bus_w(addr, bus_r(addr) | ((value << offset) & mask));
// should not do a get to verify (status register does not update
// immediately during acquisition)
if (getChipVersion() == 11) {
return pos;
}
}
// read value back
// chipv1.1, writing and reading registers are different
#ifndef VIRTUAL
if (getChipVersion() == 11) {
addr = CONFIG_V11_STATUS_REG;
mask = CONFIG_V11_STATUS_STRG_CLL_MSK;
offset = CONFIG_V11_STATUS_STRG_CLL_OFST;
}
#endif
uint32_t regval = bus_r(addr);
#ifndef VIRTUAL
// flip all contents of register //TODO FIRMWARE FIX
if (getChipVersion() == 11) {
regval ^= BIT32_MASK;
}
#endif
uint32_t retval = ((regval & mask) >> offset);
if (getChipVersion() == 11) {
// get which bit
int max = getMaxStoragecellStart();
for (int i = 0; i != max + 1; ++i) {
if (retval & (1 << i)) {
return i;
}
}
}
// chip v1.0
return retval;
}
int getMaxStoragecellStart() {
if (getChipVersion() == 11) {
return MAX_STORAGE_CELL_CHIP11_VAL;
} else {
return MAX_STORAGE_CELL_VAL;
}
}
int setNextFrameNumber(uint64_t value) {
LOG(logINFO,
@ -1075,48 +1007,6 @@ int64_t getDelayAfterTrigger() {
(1E-3 * CLK_SYNC);
}
void setNumAdditionalStorageCells(int val) {
if (val >= 0) {
LOG(logINFO, ("Setting number of addl. storage cells %d\n", val));
bus_w(CONTROL_REG,
(bus_r(CONTROL_REG) & ~CONTROL_STORAGE_CELL_NUM_MSK) |
((val << CONTROL_STORAGE_CELL_NUM_OFST) &
CONTROL_STORAGE_CELL_NUM_MSK));
}
}
int getNumAdditionalStorageCells() {
return ((bus_r(CONTROL_REG) & CONTROL_STORAGE_CELL_NUM_MSK) >>
CONTROL_STORAGE_CELL_NUM_OFST);
}
int setStorageCellDelay(int64_t val) {
if (val < 0) {
LOG(logERROR,
("Invalid delay after trigger: %lld ns\n", (long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting storage cell delay %lld ns\n", (long long int)val));
val *= (1E-3 * CLK_RUN);
bus_w(ASIC_CTRL_REG,
(bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_EXPSRE_TMR_MSK) |
((val << ASIC_CTRL_EXPSRE_TMR_OFST) & ASIC_CTRL_EXPSRE_TMR_MSK));
// validate for tolerance
int64_t retval = getStorageCellDelay();
val /= (1E-3 * CLK_RUN);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getStorageCellDelay() {
return (((int64_t)((bus_r(ASIC_CTRL_REG) & ASIC_CTRL_EXPSRE_TMR_MSK) >>
ASIC_CTRL_EXPSRE_TMR_OFST)) /
(1E-3 * CLK_RUN));
}
int64_t getNumFramesLeft() {
return get64BitReg(GET_FRAMES_LSB_REG, GET_FRAMES_MSB_REG);
}
@ -1968,18 +1858,6 @@ int64_t getComparatorDisableTime() {
return bus_r(COMP_DSBLE_TIME_REG) / (1E-3 * CLK_RUN);
}
void configureASICTimer() {
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_PRCHRG_TMR_MSK) |
ASIC_CTRL_PRCHRG_TMR_VAL);
uint32_t val = ASIC_CTRL_DS_TMR_VAL;
if (getChipVersion() == 11) {
val = ASIC_CTRL_DS_TMR_CHIP1_1_VAL;
}
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | val);
LOG(logINFO, ("Configured ASIC Timer [0x%x]\n", bus_r(ASIC_CTRL_REG)));
}
int setReadoutSpeed(int val) {
// stop state machine if running
if (runBusy()) {
@ -2601,8 +2479,7 @@ void *start_timer(void *arg) {
int transmissionDelayUs = getTransmissionDelayFrame() * 1000;
int numInterfaces = getNumberofUDPInterfaces();
int64_t periodNs = getPeriod();
int numFrames = (getNumFrames() * getNumTriggers() *
(getNumAdditionalStorageCells() + 1));
int numFrames = getNumFrames() * getNumTriggers();
int64_t expUs = getExpTime() / 1000;
const int maxPacketsPerFrame = (MAX_ROWS_PER_READOUT / ROWS_PER_PACKET);
const int dataSize = (DATA_BYTES / maxPacketsPerFrame);

17
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
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@ -44,10 +44,6 @@
#define DEFAULT_GAINMODE (DYNAMIC)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define DEFAULT_STRG_CLL_STRT_CHIP11 (0x3)
#define DEFAULT_STRG_CLL_DLY (0)
#define DEFAULT_FLIP_ROWS (0)
#define DEFAULT_FILTER_RESISTOR (1) // higher resistor
#define DEFAULT_FILTER_CELL (0)
@ -64,14 +60,11 @@
#define ROWS_PER_PACKET (8)
/* Defines in the Firmware */
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define MAX_STORAGE_CELL_VAL (15) // 0xF
#define MAX_STORAGE_CELL_CHIP11_VAL (3)
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define ACQ_TIME_MIN_CLOCK (2)
#define ASIC_FILTER_MAX_RES_VALUE (1)
#define MAX_SELECT_CHIP10_VAL (63)
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define ACQ_TIME_MIN_CLOCK (2)
#define ASIC_FILTER_MAX_RES_VALUE (1)
#define MAX_SELECT_CHIP10_VAL (63)
#define MAX_PHASE_SHIFTS (240)
#define BIT16_MASK (0xFFFF)

6
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
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@ -222,7 +222,7 @@ int getReadoutMode();
#endif
// parameters - timer
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
int selectStoragecellStart(int pos);
int getMaxStoragecellStart();
#endif
@ -266,7 +266,7 @@ int64_t getSubDeadTime();
int64_t getMeasuredPeriod();
int64_t getMeasuredSubPeriod();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
void setNumAdditionalStorageCells(int val);
int getNumAdditionalStorageCells();
int setStorageCellDelay(int64_t val);
@ -513,7 +513,9 @@ void configureChip();
int autoCompDisable(int on);
int setComparatorDisableTime(int64_t val);
int64_t getComparatorDisableTime();
#ifndef MOENCHD
void configureASICTimer();
#endif
int setReadoutSpeed(int val);
int getReadoutSpeed(int *retval);
int setPhase(enum CLKINDEX ind, int val, int degrees);

12
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
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@ -2158,7 +2158,7 @@ int get_num_additional_storage_cells(int file_des) {
memset(mess, 0, sizeof(mess));
int retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(JUNGFRAUD)
functionNotImplemented();
#else
// get only
@ -2177,7 +2177,7 @@ int set_num_additional_storage_cells(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Setting number of addl. storage cells %d\n", arg));
#if !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(JUNGFRAUD)
functionNotImplemented();
#else
// only set
@ -2620,7 +2620,7 @@ int get_storage_cell_delay(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(JUNGFRAUD)
functionNotImplemented();
#else
// get only
@ -2647,7 +2647,7 @@ int set_storage_cell_delay(int file_des) {
LOG(logDEBUG1,
("Setting storage cell delay %lld ns\n", (long long int)arg));
#if !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(JUNGFRAUD)
functionNotImplemented();
#else
// only set
@ -4015,7 +4015,7 @@ int storage_cell_start(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Setting Storage cell start to %d\n", arg));
#if !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(JUNGFRAUD)
functionNotImplemented();
#else
// set & get
@ -6958,7 +6958,7 @@ int get_receiver_parameters(int file_des) {
return printSocketReadError();
// additional storage cells
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
i32 = getNumAdditionalStorageCells();
#else
i32 = 0;