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m3 and g2: change in system clock (clkdiv2) should also change the time settings(exptime, period, gate delay etc.), g2: sys freq same irrespective of external or internal timing source (#470)
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@ -75,6 +75,8 @@ This document describes the differences between v7.0.0 and v6.x.x
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- rxr src files and classes (detectordata, ZmqSocket, helpDacs) added to sls namespace, and macros (namely from logger (logINFO etc)), slsDetectorGui (make_unique in implemtnation requires sls nemspace (points to std otherwise) but not deectorImpl.cpp)
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- blackfin programing made seamless (nCE fixed which helps)
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-save settings file for m3 and eiger
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- g2 and m3 clkdiv 2 (system clock) change should affect time settings (g2: exptime, period, delayaftertrigger, burstperiod, m3: exptime, gatedelay, gateperiod, period, delayaftertrigger)
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- g2 system frequency is the same irrespective of timing source
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2. Resolved Issues
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==================
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@ -2297,6 +2297,24 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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setPhase(i, oldPhases[i], 1);
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}
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}
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// update system frequency and time settings that depend on it
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if (ind == SYSTEM_C0) {
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LOG(logINFO, ("\tUpdating time settings (sys freq change)\n"));
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int64_t exptime = getExpTime();
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int64_t period = getPeriod();
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int64_t delayAfterTrigger = getDelayAfterTrigger();
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int64_t burstPeriod = getBurstPeriod();
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systemFrequency = ((double)getVCOFrequency(SYSTEM_C0) /
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(double)clkDivider[SYSTEM_C0]);
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setExpTime(exptime);
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setPeriod(period);
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setDelayAfterTrigger(delayAfterTrigger);
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setBurstPeriod(burstPeriod);
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LOG(logINFO, ("\tDone updating time settings\n"));
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}
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return OK;
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}
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@ -2798,13 +2816,10 @@ void setTimingSource(enum timingSourceType value) {
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case TIMING_INTERNAL:
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LOG(logINFO, ("Setting timing source to internal\n"));
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bus_w(addr, (bus_r(addr) & ~CONTROL_TIMING_SOURCE_EXT_MSK));
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systemFrequency = INT_SYSTEM_C0_FREQUENCY;
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break;
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case TIMING_EXTERNAL:
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LOG(logINFO, ("Setting timing source to exernal\n"));
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bus_w(addr, (bus_r(addr) | CONTROL_TIMING_SOURCE_EXT_MSK));
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systemFrequency = ((double)getVCOFrequency(SYSTEM_C0) /
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(double)clkDivider[SYSTEM_C0]);
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break;
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default:
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LOG(logERROR, ("Unknown timing source %d\n", value));
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@ -1331,7 +1331,7 @@ int setTrimbits(int *trimbits) {
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uint32_t prevRunClk = clkDivider[SYSTEM_C0];
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// set to trimming clock
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if (setClockDivider(SYSTEM_C0, DEFAULT_TRIMMING_RUN_CLKDIV) == FAIL) {
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if (setClockDividerWithTimeUpdateOption(SYSTEM_C0, DEFAULT_TRIMMING_RUN_CLKDIV, 0) == FAIL) {
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LOG(logERROR,
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("Could not start trimming. Could not set to trimming clock\n"));
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return FAIL;
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@ -1364,7 +1364,7 @@ int setTrimbits(int *trimbits) {
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}
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// set back to previous clock
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if (setClockDivider(SYSTEM_C0, prevRunClk) == FAIL) {
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if (setClockDividerWithTimeUpdateOption(SYSTEM_C0, prevRunClk, 0) == FAIL) {
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LOG(logERROR, ("Could not set to previous run clock after trimming\n"));
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return FAIL;
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}
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@ -2215,6 +2215,10 @@ int getVCOFrequency(enum CLKINDEX ind) {
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int getMaxClockDivider() { return ALTERA_PLL_C10_GetMaxClockDivider(); }
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int setClockDivider(enum CLKINDEX ind, int val) {
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return setClockDividerWithTimeUpdateOption(ind, val, 1);
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}
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int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val, int timeUpdate) {
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if (ind < 0 || ind >= NUM_CLOCKS) {
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LOG(logERROR, ("Unknown clock index %d to set clock divider\n", ind));
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return FAIL;
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@ -2239,6 +2243,32 @@ int setClockDivider(enum CLKINDEX ind, int val) {
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int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
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int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
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ALTERA_PLL_C10_SetOuputClockDivider(pllIndex, clkIndex, val);
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// Update time settings that depend on system frequency
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// timeUpdate = 0 for setChipRegister/setTrimbits etc
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// as clk reverted back again
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if (timeUpdate && ind == SYSTEM_C0) {
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LOG(logINFO, ("\tUpdating time settings (sys freq change)\n"));
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int64_t exptime[3] = {0, 0, 0};
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int64_t gateDelay[3] = {0, 0, 0};
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for (int i = 0; i != 3; ++i) {
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exptime[i] = getExpTime(i);
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gateDelay[i] = getGateDelay(i);
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}
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int64_t period = getPeriod();
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int64_t delayAfterTrigger = getDelayAfterTrigger();
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clkDivider[ind] = val;
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for (int i = 0; i != 3; ++i) {
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setExpTime(i, exptime[i]);
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setGateDelay(i, gateDelay[i]);
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}
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setPeriod(period);
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setDelayAfterTrigger(delayAfterTrigger);
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LOG(logINFO, ("\tDone updating time settings\n"));
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}
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clkDivider[ind] = val;
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LOG(logINFO, ("\t%s clock (%d) divider set to %d\n", clock_names[ind], ind,
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clkDivider[ind]));
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@ -2629,7 +2659,7 @@ int setChipStatusRegister(int csr) {
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uint32_t prevRunClk = clkDivider[SYSTEM_C0];
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// set to trimming clock
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if (setClockDivider(SYSTEM_C0, DEFAULT_TRIMMING_RUN_CLKDIV) == FAIL) {
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if (setClockDividerWithTimeUpdateOption(SYSTEM_C0, DEFAULT_TRIMMING_RUN_CLKDIV, 0) == FAIL) {
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LOG(logERROR,
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("Could not set to trimming clock in order to change CSR\n"));
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return FAIL;
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@ -2651,7 +2681,7 @@ int setChipStatusRegister(int csr) {
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}
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// set back to previous clock
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if (setClockDivider(SYSTEM_C0, prevRunClk) == FAIL) {
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if (setClockDividerWithTimeUpdateOption(SYSTEM_C0, prevRunClk, 0) == FAIL) {
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LOG(logERROR,
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("Could not set to previous run clock after changing CSR\n"));
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return FAIL;
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@ -565,6 +565,7 @@ int getFrequency(enum CLKINDEX ind);
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int getVCOFrequency(enum CLKINDEX ind);
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int getMaxClockDivider();
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int setClockDivider(enum CLKINDEX ind, int val);
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int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val, int timeUpdate);
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int getClockDivider(enum CLKINDEX ind);
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#elif GOTTHARD2D
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@ -7,8 +7,8 @@
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#define APIGUI 0x220328
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#define APICTB 0x220524
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#define APIGOTTHARD 0x220524
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#define APIGOTTHARD2 0x220524
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#define APIJUNGFRAU 0x220524
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#define APIMYTHEN3 0x220524
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#define APIMOENCH 0x220519
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#define APIEIGER 0x220524
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#define APIMYTHEN3 0x220602
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#define APIGOTTHARD2 0x220602
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