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ctb server: removed unnecessary prints, resulting in a bug fix for slow adc temp

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This commit is contained in:
maliakal_d 2019-02-22 13:53:59 +01:00
parent a1a6a5dbaa
commit 20edf61e30
5 changed files with 50 additions and 32 deletions
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2
slsDetectorServers/slsDetectorServer/AD7689.h
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@ -103,7 +103,7 @@ void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clk
void AD7689_Disable() {
bus_w(AD7689_Reg, (bus_r(AD7689_Reg)
&~(AD7689_CnvMask)
| AD7689_ClkMask
&~AD7689_ClkMask
&~(AD7689_DigMask)));
}

44
slsDetectorServers/slsDetectorServer/I2C.h
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@ -167,31 +167,31 @@ void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
* @returns value read from register
*/
uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
FILE_LOG(logDEBUG1, (" ================================================\n"));
FILE_LOG(logDEBUG1, (" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
FILE_LOG(logDEBUG2, (" ================================================\n"));
FILE_LOG(logDEBUG2, (" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
FILE_LOG(logDEBUG1, (" devId:0x%x\n", devIdMask));
FILE_LOG(logDEBUG2, (" devId:0x%x\n", devIdMask));
// write I2C ID
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
FILE_LOG(logDEBUG1, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
FILE_LOG(logDEBUG2, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
// write register addr
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
FILE_LOG(logDEBUG1, (" write addr:0x%x\n", addr));
FILE_LOG(logDEBUG2, (" write addr:0x%x\n", addr));
// repeated start with read (repeated start needed here because it was in write operation mode earlier, for the device ID)
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
FILE_LOG(logDEBUG1, (" repeated start:0x%x\n", (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
FILE_LOG(logDEBUG2, (" repeated start:0x%x\n", (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
// continue reading
bus_w(I2C_Transfer_Command_Fifo_Reg, 0x0);
FILE_LOG(logDEBUG1, (" continue reading:0x%x\n", 0x0));
FILE_LOG(logDEBUG2, (" continue reading:0x%x\n", 0x0));
// stop reading
bus_w(I2C_Transfer_Command_Fifo_Reg, I2C_TFR_CMD_STOP_MSK);
FILE_LOG(logDEBUG1, (" stop reading:0x%x\n", I2C_TFR_CMD_STOP_MSK));
FILE_LOG(logDEBUG2, (" stop reading:0x%x\n", I2C_TFR_CMD_STOP_MSK));
// read value
uint32_t retval = 0;
@ -201,24 +201,24 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
int status = 1;
while(status) {
status = bus_r(I2C_Status_Reg) & I2C_STATUS_BUSY_MSK;
FILE_LOG(logDEBUG1, (" status:%d\n", status));
FILE_LOG(logDEBUG2, (" status:%d\n", status));
usleep(0);
}
// get rx fifo level (get number of bytes to be received)
int level = bus_r(I2C_Rx_Data_Fifo_Level_Reg);
FILE_LOG(logDEBUG1, (" level:%d\n", level));
FILE_LOG(logDEBUG2, (" level:%d\n", level));
int iloop = level - 1;
// level bytes to read, read 1 byte at a time
for (iloop = level - 1; iloop >= 0; --iloop) {
u_int16_t byte = bus_r(I2C_Rx_Data_Fifo_Reg) & I2C_RX_DATA_FIFO_RXDATA_MSK;
FILE_LOG(logDEBUG1, (" byte nr %d:0x%x\n", iloop, byte));
FILE_LOG(logDEBUG2, (" byte nr %d:0x%x\n", iloop, byte));
// push by 1 byte at a time
retval |= (byte << (8 * iloop));
}
FILE_LOG(logDEBUG1, (" retval:0x%x\n", retval));
FILE_LOG(logDEBUG1, (" ================================================\n"));
FILE_LOG(logDEBUG2, (" retval:0x%x\n", retval));
FILE_LOG(logDEBUG2, (" ================================================\n"));
return retval;
}
@ -229,34 +229,34 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
* @param data data to be written (16 bit)
*/
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data) {
FILE_LOG(logDEBUG1, (" ================================================\n"));
FILE_LOG(logDEBUG1, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId, addr, data));
FILE_LOG(logDEBUG2, (" ================================================\n"));
FILE_LOG(logDEBUG2, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId, addr, data));
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
FILE_LOG(logDEBUG1, (" devId:0x%x\n", devId));
FILE_LOG(logDEBUG2, (" devId:0x%x\n", devId));
// write I2C ID
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
FILE_LOG(logDEBUG1, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
FILE_LOG(logDEBUG2, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
// write register addr
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
FILE_LOG(logDEBUG1, (" write addr:0x%x\n", addr));
FILE_LOG(logDEBUG2, (" write addr:0x%x\n", addr));
// do not do the repeated start as it is already in write operation mode (else it wont work)
uint8_t msb = (uint8_t)((data & 0xFF00) >> 8);
uint8_t lsb = (uint8_t)(data & 0x00FF);
FILE_LOG(logDEBUG1, (" msb:0x%02x, lsb:0x%02x\n", msb, lsb));
FILE_LOG(logDEBUG2, (" msb:0x%02x, lsb:0x%02x\n", msb, lsb));
// writing data MSB
bus_w(I2C_Transfer_Command_Fifo_Reg, ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
FILE_LOG(logDEBUG1, (" write msb:0x%02x\n", ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
FILE_LOG(logDEBUG2, (" write msb:0x%02x\n", ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
// writing data LSB and stop writing bit
bus_w(I2C_Transfer_Command_Fifo_Reg, ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK);
FILE_LOG(logDEBUG1, (" write lsb and stop writing:0x%x\n", ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK));
FILE_LOG(logDEBUG1, (" ================================================\n"));
FILE_LOG(logDEBUG2, (" write lsb and stop writing:0x%x\n", ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK));
FILE_LOG(logDEBUG2, (" ================================================\n"));
}

2
slsDetectorServers/slsDetectorServer/LTC2620.h
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@ -154,7 +154,7 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
// select all chips (ctb daisy chain; others 1 chip)
FILE_LOG(logDEBUG2, ("Selecting LTC2620\n"));
SPIChipSelect (&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask, LTC2620_DigMask);
SPIChipSelect (&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask, LTC2620_DigMask, 0);
// send same data to all
if (chipIndex < 0) {

32
slsDetectorServers/slsDetectorServer/commonServerFunctions.h
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@ -1,16 +1,25 @@
#pragma once
#include "blackfin.h"
#include <unistd.h> // usleep
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask) {
FILE_LOG(logDEBUG2, ("SPI chip select. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x\n",
*valw, addr, csmask, clkmask, digoutmask));
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit) {
FILE_LOG(logDEBUG2, ("SPI chip select. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
// needed for the slow adcs for apprx 20 ns before and after rising of convbit (usleep val is vague assumption)
if (convBit)
usleep(20);
// start point
(*valw) = ((bus_r(addr) | csmask | clkmask) &(~digoutmask));
bus_w (addr, (*valw));
FILE_LOG(logDEBUG2, ("startpoint. valw:0x%08x\n", *valw));
// needed for the slow adcs for apprx 10 ns before and after rising of convbit (usleep val is vague assumption)
if (convBit)
usleep(10);
// chip sel bar down
(*valw) &= ~csmask;
bus_w (addr, (*valw));
@ -19,14 +28,22 @@ void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t cl
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit) {
FILE_LOG(logDEBUG2, ("SPI chip deselect. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x\n",
*valw, addr, csmask, clkmask));
FILE_LOG(logDEBUG2, ("SPI chip deselect. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
// needed for the slow adcs for apprx 20 ns before and after rising of convbit (usleep val is vague assumption)
if (convBit)
usleep(20);
// chip sel bar up
(*valw) |= csmask;
bus_w (addr, (*valw));
FILE_LOG(logDEBUG2, ("chip sel bar up. valw:0x%08x\n", *valw));
// needed for the slow adcs for apprx 10 ns before and after rising of convbit (usleep val is vague assumption)
if (convBit)
usleep(10);
//clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
@ -34,6 +51,7 @@ void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t
// stop point = start point of course
(*valw) &= ~digoutmask;
// slow adcs use convBit (has to go high and then low) instead of csmask
if (convBit) {
(*valw) &= ~csmask;
} else {
@ -101,7 +119,7 @@ void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstos
}
uint32_t valw;
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask);
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask, convBit);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
@ -112,7 +130,7 @@ uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive,
uint32_t valw;
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask);
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask, convBit);
uint32_t retval = receiveDataFromSPI(&valw, addr, numbitstoreceive, clkmask, readaddr);

2
slsDetectorSoftware/slsDetector/slsDetectorCommand.cpp
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@ -4097,7 +4097,7 @@ std::string slsDetectorCommand::cmdADC(int narg, char *args[], int action, int d
//if ((adc == TEMPERATURE_ADC) || (adc == TEMPERATURE_FPGA))
if (adc < 100 || adc == SLOW_ADC_TEMP)
strcat(answer," °C");
strcat(answer,"°C");
else if (adc == I_POWER_A || adc == I_POWER_B || adc == I_POWER_C || adc == I_POWER_D || adc == I_POWER_IO)
strcat(answer," mA");
else