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clang and redoing copy detector server to have a soft link and put that in respawning for blackfin servers

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This commit is contained in:
maliakal_d
2021-10-18 17:17:56 +02:00
parent 43bbf66e85
commit 203d6465a1
11 changed files with 414 additions and 322 deletions
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84
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -8,6 +8,8 @@
#define REQRD_FRMWRE_VRSN_BOARD2 0x210831 // 1.0 pcb (version = 010)
#define REQRD_FRMWRE_VRSN 0x211008 // 2.0 pcb (version = 011)
#define LINKED_SERVER_NAME "jungfrauDetectorServer"
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Struct Definitions */
@ -65,9 +67,9 @@ enum DACINDEX {
420 /* J_VREF_COMP */ \
};
#define NUMSETTINGS (2)
#define NSPECIALDACS (3)
#define SPECIALDACINDEX {J_VREF_PRECH, J_VREF_DS, J_VREF_COMP};
#define NUMSETTINGS (2)
#define NSPECIALDACS (3)
#define SPECIALDACINDEX {J_VREF_PRECH, J_VREF_DS, J_VREF_COMP};
#define SPECIAL_DEFAULT_DYNAMIC_GAIN_VALS \
{ 1450, 480, 420 }
#define SPECIAL_DEFAULT_DYNAMICHG0_GAIN_VALS \
@ -111,20 +113,20 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define DEFAULT_FILTER_RESISTOR (1) // higher resistor
#define DEFAULT_FILTER_CELL (0)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define MAX_FILTER_CELL_VAL (12)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define MAX_FILTER_CELL_VAL (12)
#define MIN_ROWS_PER_READOUT (8)
#define MAX_ROWS_PER_READOUT (512)
#define READ_N_ROWS_MULTIPLE (8) //512 rows/128packets * 2 interfaces
#define READ_N_ROWS_MULTIPLE (8) // 512 rows/128packets * 2 interfaces
/* Defines in the Firmware */
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define MAX_STORAGE_CELL_VAL (15) // 0xF
#define MAX_STORAGE_CELL_CHIP11_VAL (3)
#define MAX_STORAGE_CELL_CHIP11_VAL (3)
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define ACQ_TIME_MIN_CLOCK (2)
#define ASIC_FILTER_MAX_RES_VALUE (1)
@ -137,32 +139,28 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
// 2.0 pcb (chipv1.1)
#define SAMPLE_ADC_FULL_SPEED_CHIP11 \
#define SAMPLE_ADC_FULL_SPEED_CHIP11 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x0000
#define SAMPLE_ADC_HALF_SPEED_CHIP11 \
#define SAMPLE_ADC_HALF_SPEED_CHIP11 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1110
#define SAMPLE_ADC_QUARTER_SPEED_CHIP11 \
#define SAMPLE_ADC_QUARTER_SPEED_CHIP11 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2230
#define ADC_PHASE_FULL_SPEED_CHIP11 (160)
#define ADC_PHASE_HALF_SPEED_CHIP11 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP11 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP11 (75)
#define DBIT_PHASE_HALF_SPEED_CHIP11 (135)
#define DBIT_PHASE_QUARTER_SPEED_CHIP11 (135)
#define ADC_OFST_FULL_SPEED_VAL_CHIP11 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP11 (0x08)
#define ADC_OFST_QUARTER_SPEED_VAL_CHIP11 (0x04)
#define ADC_PHASE_FULL_SPEED_CHIP11 (160)
#define ADC_PHASE_HALF_SPEED_CHIP11 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP11 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP11 (75)
#define DBIT_PHASE_HALF_SPEED_CHIP11 (135)
#define DBIT_PHASE_QUARTER_SPEED_CHIP11 (135)
#define ADC_OFST_FULL_SPEED_VAL_CHIP11 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP11 (0x08)
#define ADC_OFST_QUARTER_SPEED_VAL_CHIP11 (0x04)
// 2.0 pcb (chipv1.0)
#define SAMPLE_ADC_FULL_SPEED_CHIP10 \
@ -175,19 +173,17 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define ADC_PHASE_FULL_SPEED_CHIP10 (160)
#define ADC_PHASE_HALF_SPEED_CHIP10 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP10 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP10 (100)
#define DBIT_PHASE_HALF_SPEED_CHIP10 (150)
#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (150)
#define ADC_OFST_FULL_SPEED_VAL_CHIP10 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP10 (0x08)
#define ADC_OFST_QUARTER_SPEED_VAL_CHIP10 (0x04)
#define ADC_PHASE_FULL_SPEED_CHIP10 (160)
#define ADC_PHASE_HALF_SPEED_CHIP10 (160)
#define ADC_PHASE_QUARTER_SPEED_CHIP10 (160)
#define DBIT_PHASE_FULL_SPEED_CHIP10 (100)
#define DBIT_PHASE_HALF_SPEED_CHIP10 (150)
#define DBIT_PHASE_QUARTER_SPEED_CHIP10 (150)
#define ADC_OFST_FULL_SPEED_VAL_CHIP10 (0x10)
#define ADC_OFST_HALF_SPEED_VAL_CHIP10 (0x08)
#define ADC_OFST_QUARTER_SPEED_VAL_CHIP10 (0x04)
// 1.0 pcb (2 resistor network)
#define SAMPLE_ADC_HALF_SPEED_BOARD2 \
@ -197,11 +193,11 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2610
#define ADC_PHASE_HALF_SPEED_BOARD2 (110)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220)
#define ADC_PHASE_HALF_SPEED_BOARD2 (110)
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220)
#define DBIT_PHASE_HALF_SPEED_BOARD2 (150)
#define DBIT_PHASE_QUARTER_SPEED_BOARD2 (150)
#define DBIT_PHASE_HALF_SPEED_BOARD2 (150)
#define DBIT_PHASE_QUARTER_SPEED_BOARD2 (150)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x10)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x08)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x10)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x08)