detectors/slsDetectorPackage
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speed separated

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This commit is contained in:
maliakal_d
2019-11-05 18:50:35 +01:00
parent 96d64778ee
commit 1f64d2a4e2
29 changed files with 830 additions and 714 deletions
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BIN
slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer
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42
slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
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@ -450,7 +450,7 @@ void setupDetector() {
setParallelMode(DEFAULT_PARALLEL_MODE);
setOverFlowMode(DEFAULT_READOUT_STOREINRAM_MODE);
setStoreInRamMode(DEFAULT_READOUT_OVERFLOW32_MODE);
setSpeed(CLOCK_DIVIDER, DEFAULT_CLK_SPEED);//clk_devider,half speed
setClockDivider(RUN_CLK, DEFAULT_CLK_SPEED);//clk_devider,half speed
setIODelay(DEFAULT_IO_DELAY);
setTiming(DEFAULT_TIMING_MODE);
setStartingFrameNumber(DEFAULT_STARTING_FRAME_NUMBER);
@ -532,25 +532,6 @@ int setDynamicRange(int dr) {
/* parameters - readout */
void setSpeed(enum speedVariable ind, int val) {
if (ind != CLOCK_DIVIDER)
return;
if (val != -1) {
FILE_LOG(logDEBUG1, ("Setting Read out Speed: %d\n", val));
#ifndef VIRTUAL
if (Feb_Control_SetReadoutSpeed(val))
#endif
eiger_readoutspeed = val;
}
}
int getSpeed(enum speedVariable ind) {
if (ind != CLOCK_DIVIDER)
return -1;
return eiger_readoutspeed;
}
int setParallelMode(int mode) {
mode = (mode == 0 ? E_NON_PARALLEL : E_PARALLEL);
#ifndef VIRTUAL
@ -1354,6 +1335,27 @@ int enableTenGigabitEthernet(int val) {
/* eiger specific - iodelay, pulse, rate, temp, activate, delay nw parameter */
int setClockDivider(enum CLKINDEX ind, int val) {
if (ind != RUN_CLK) {
FILE_LOG(logERROR, ("Unknown clock index: %d\n", ind));
return FAIL;
}
if (val >= 0) {
FILE_LOG(logINFO, ("Setting Read out Speed: %d\n", val));
#ifndef VIRTUAL
if (Feb_Control_SetReadoutSpeed(val))
#endif
eiger_readoutspeed = val;
}
}
int getClockDivider(enum CLKINDEX ind) {
if (ind != RUN_CLK) {
FILE_LOG(logERROR, ("Unknown clock index: %d\n", ind));
return FAIL;
}
return eiger_readoutspeed;
}
int setIODelay(int val) {
if (val!=-1) {

4
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -30,7 +30,9 @@ enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_L
};
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
enum {E_PARALLEL, E_NON_PARALLEL};
enum ROINDEX {E_PARALLEL, E_NON_PARALLEL};
enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define CLK_NAMES "run"
/* Hardware Definitions */
#define NCHAN (256 * 256)