mythen3, gotthard2: change phase, change freq bugfix

This commit is contained in:
maliakal_d 2019-11-19 17:57:28 +01:00
parent 1539326fda
commit 1cea6af590
4 changed files with 6 additions and 6 deletions

View File

@ -88,7 +88,7 @@ int ALTERA_PLL_C10_Reconfigure(int pllIndex) {
// write anything to base address to start reconfiguring
FILE_LOG(logDEBUG1, ("\tWriting 1 to base address 0x%x to start reconfiguring\n", ALTERA_PLL_C10_BaseAddress[pllIndex]));
//bus_w_csp1(ALTERA_PLL_C10_BaseAddress[pllIndex], 0x1);
bus_w_csp1(ALTERA_PLL_C10_BaseAddress[pllIndex], 0x1);
// wait for write operation to be completed by polling wait request bit
int ret = OK;
@ -143,7 +143,7 @@ int ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos)
uint32_t value = (((phaseToDo << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK) |
(pos ? ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL));
FILE_LOG(logDEBUG1, ("\t[addr:0x%x, phaseTodo:%d phaseleft:%d phase word:0x%08x]\n", addr, phaseToDo, phase, value));
//bus_w_csp1(addr, value);
bus_w_csp1(addr, value);
if (ALTERA_PLL_C10_Reconfigure(pllIndex) == FAIL) {
ret = FAIL;
@ -182,11 +182,11 @@ int ALTERA_PLL_C10_SetOuputFrequency (int pllIndex, int clkIndex, int value) {
FILE_LOG(logDEBUG1, ("\t[addr:0x%x, word:0x%08x]\n", addr, val));
// write frequency
//bus_w_csp1(addr, val);
bus_w_csp1(addr, val);
int ret = ALTERA_PLL_C10_Reconfigure(pllIndex);
// reset required to keep the phase relationships (must reconfigure adcs again after this as adc clock is stopped temporarily when resetting pll)
// reset required to keep the phase relationships
ALTERA_PLL_C10_ResetPLL (pllIndex);
return ret;

View File

@ -8,5 +8,5 @@
#define APIGOTTHARD 0x191111
#define APIJUNGFRAU 0x191111
#define APIEIGER 0x191111
#define APIGOTTHARD2 0x191115
#define APIMYTHEN3 0x191118
#define APIMYTHEN3 0x191119
#define APIGOTTHARD2 0x191119