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moench basic tearing down

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This commit is contained in:
maliakal_d
2019-01-11 15:19:08 +01:00
parent 363f4f1da0
commit 1941e90697
5 changed files with 54 additions and 50 deletions
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18
slsDetectorServers/moenchDetectorServer/RegisterDefs.h
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@ -86,8 +86,8 @@
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//0xCACA#define FIFO_DATA_WRD_OFST (16)
//0xCACA#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
@ -515,13 +515,13 @@
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
/** I2C Control register */
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
//fixme: upto 0x10f
//#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT) // in FW, but not used anywhere

12
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -516,7 +516,6 @@ void setupDetector() {
setTimer(CYCLES_NUMBER, DEFAULT_NUM_CYCLES);
setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY);
selectStoragecellStart(DEFAULT_STRG_CLL_STRT);
setTiming(DEFAULT_TIMING_MODE);
// send via tcp (moench via udp with configuremac)
@ -860,17 +859,6 @@ enum readOutFlags setReadOutFlags(enum readOutFlags val) {
/* parameters - timer */
int selectStoragecellStart(int pos) {
if (pos >= 0) {
FILE_LOG(logINFO, ("Setting storage cell start: %d\n", pos));
bus_w(DAQ_REG, bus_r(DAQ_REG) & ~DAQ_STRG_CELL_SLCT_MSK);
bus_w(DAQ_REG, bus_r(DAQ_REG) | ((pos << DAQ_STRG_CELL_SLCT_OFST) & DAQ_STRG_CELL_SLCT_MSK));
}
return ((bus_r(DAQ_REG) & DAQ_STRG_CELL_SLCT_MSK) >> DAQ_STRG_CELL_SLCT_OFST);
}
int64_t setTimer(enum timerIndex ind, int64_t val) {
int64_t retval = -1;

5
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
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@ -26,10 +26,7 @@ typedef struct ip_header_struct {
/* Enums */
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8};
/* Hardware Definitions */
#define NCHAN (36)