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G2clkdiv (#547)
* g2 changing clkdivs 2 3 4 to defaults for burst and cw mode
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@ -65,6 +65,14 @@
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#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
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#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
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#define DEFAULT_CNTNS_SYSTEM_C0 (10) // (72222224) run_clk, 72 MHz
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#define DEFAULT_CNTNS_SYSTEM_C1 (20) // (36111112) chip_clk, 36 MHz
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#define DEFAULT_CNTNS_SYSTEM_C2 (10) // (72222224) sync_clk, 72 MHz
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#define DEFAULT_BURST_SYSTEM_C0 (5) // (144444448) run_clk, 144 MHz
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#define DEFAULT_BURST_SYSTEM_C1 (10) // (72222224) chip_clk, 72 MHz
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#define DEFAULT_BURST_SYSTEM_C2 (5) // (144444448) sync_clk, 144 MHz
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#define DEFAULT_READOUT_SPEED (G2_108MHZ)
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#define SPEED_144_CLKDIV_0 (6)
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#define SPEED_144_CLKDIV_1 (6)
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