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gotthard2: timingsource and currentsource features, (timing source external yet to be implemented in fpga to test (#80)

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This commit is contained in:
Dhanya Thattil
2020-02-28 12:45:02 +01:00
committed by GitHub
parent 2e2e91b219
commit 11e7737a2f
17 changed files with 334 additions and 3 deletions
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4
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
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@ -104,6 +104,8 @@
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
#define CONTROL_TIMING_SOURCE_EXT_MSK (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
@ -128,6 +130,8 @@
#define ASIC_CONFIG_FIX_GAIN_1_VAL ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DONE_OFST (31)

BIN
slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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40
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -447,6 +447,8 @@ void setupDetector() {
setDelayAfterTrigger(DEFAULT_DELAY_AFTER_TRIGGER);
setBurstPeriod(DEFAULT_BURST_PERIOD);
setTiming(DEFAULT_TIMING_MODE);
setCurrentSource(DEFAULT_CURRENT_SOURCE);
setTimingSource(DEFAULT_TIMING_SOURCE);
}
int readConfigFile() {
@ -1961,6 +1963,44 @@ enum burstMode getBurstMode() {
return burstMode;
}
void setCurrentSource(int value) {
uint32_t addr = ASIC_CONFIG_REG;
if (value > 0) {
bus_w(addr, (bus_r(addr) | ASIC_CONFIG_CURRENT_SRC_EN_MSK));
} else if (value == 0) {
bus_w(addr, (bus_r(addr) &~ ASIC_CONFIG_CURRENT_SRC_EN_MSK));
}
}
int getCurrentSource() {
return ((bus_r(ASIC_CONFIG_REG) & ASIC_CONFIG_CURRENT_SRC_EN_MSK) >> ASIC_CONFIG_CURRENT_SRC_EN_OFST);
}
void setTimingSource(enum timingSourceType value) {
uint32_t addr = CONTROL_REG;
switch (value) {
case TIMING_INTERNAL:
FILE_LOG(logINFO, ("Setting timing source to internal\n"));
bus_w(addr, (bus_r(addr) &~ CONTROL_TIMING_SOURCE_EXT_MSK));
break;
case TIMING_EXTERNAL:
FILE_LOG(logINFO, ("Setting timing source to exernal\n"));
bus_w(addr, (bus_r(addr) | CONTROL_TIMING_SOURCE_EXT_MSK));
break;
default:
FILE_LOG(logERROR, ("Unknown timing source %d\n", value));
break;
}
}
enum timingSourceType getTimingSource() {
if (bus_r(CONTROL_REG) & CONTROL_TIMING_SOURCE_EXT_MSK) {
return TIMING_EXTERNAL;
}
return TIMING_INTERNAL;
}
/* aquisition */

3
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
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@ -41,6 +41,9 @@
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_CURRENT_SOURCE (0)
#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz
#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz
#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz