mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-21 19:30:03 +02:00
Xilinxctb/update reg (#1084)
* updated RegisterDefs.h from firmware update * Revert "updated RegisterDefs.h from firmware update" This reverts commit 64f1b2546e742f0b0513124a599cd9bcde11760c. * updated registers and had it formatted * Revert "updated registers and had it formatted" This reverts commit 1641b705b0d8616bcff4a5cd796d8796d09391f2. * udpated registers from firmware, reading config file in server (chip config, reset chip, enable_clock_pattern) specific for matterhorn,this is done when powering on chip, removed startreadout, fixed status register bits, updated firmware version * fix for patioctrl allowed for zxilinx and adding readout pattern for scientists that like to push the acquire button * fixing default enable clock and readout pattern for xilinx (patioctrl has to be 32 bit) * Xilinxctb/first image (#1094) * reduce xilinxCTB readout done checks to single register, increased clockEna pattern limits, clear FPGA FiFos and counters on powerchip, disable counters 1-3 in matterhorn configuration * change print of xilinxctb server * remove acquisition done check --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> * binary xilinx in * formatting * added reset of udp buffer FIFO to xilinxCTB --------- Co-authored-by: Martin Mueller <72937414+mmarti04@users.noreply.github.com> Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
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e933a25453
commit
117637863d
@ -197,6 +197,8 @@ int isChipConfigured();
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int powerChip(int on, char *mess);
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int getPowerChip();
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int configureChip(char *mess);
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int readConfigFile(char *mess, char *fileName, char *fileType);
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int resetChip(char *mess);
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#endif
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#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
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defined(MYTHEN3D) || defined(GOTTHARD2D)
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@ -742,8 +744,7 @@ int softwareTrigger();
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#if defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)
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int softwareTrigger(int block);
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#endif
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#if defined(EIGERD) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || \
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defined(XILINX_CHIPTESTBOARDD)
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#if defined(EIGERD) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD)
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int startReadOut();
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#endif
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enum runStatus getRunStatus();
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@ -853,7 +853,7 @@ int loadPattern(char *message, enum TLogLevel printLevel,
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}
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}
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// iocontrol
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#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) // TODO
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#if !defined(MYTHEN3D)
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if (ret == OK) {
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ret = validate_writePatternIOControl(message, pat->ioctrl);
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}
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@ -914,7 +914,7 @@ int getPattern(char *message, patternParameters *pat) {
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pat->word[i] = retval64;
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}
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// iocontrol
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#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) // TODO
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#if !defined(MYTHEN3D)
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if (ret == OK) {
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validate_readPatternIOControl();
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}
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@ -1051,12 +1051,12 @@ int loadPatternFile(char *patFname, char *errMessage) {
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}
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// patioctrl
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#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) // TODO
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#if !defined(MYTHEN3D) // TODO
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if (!strncmp(line, "patioctrl", strlen("patioctrl"))) {
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uint64_t arg = 0;
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// cannot scan values
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#ifdef VIRTUAL
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#if defined(VIRTUAL) || defined(XILINX_CHIPTESTBOARDD)
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if (sscanf(line, "%s 0x%lx", command, &arg) != 2) {
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#else
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if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
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@ -8467,8 +8467,7 @@ int get_bursts_left(int file_des) {
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int start_readout(int file_des) {
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ret = OK;
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memset(mess, 0, sizeof(mess));
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#if !defined(MYTHEN3D) && !defined(CHIPTESTBOARDD) && \
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!defined(XILINX_CHIPTESTBOARDD)
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#if !defined(MYTHEN3D) && !defined(CHIPTESTBOARDD)
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functionNotImplemented();
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#else
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if (Server_VerifyLock() == OK) {
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@ -40,3 +40,9 @@ set_target_properties(xilinx_ctbDetectorServer_virtual PROPERTIES
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install(TARGETS xilinx_ctbDetectorServer_virtual
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RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
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)
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configure_file(chip_config_xilinx.txt ${CMAKE_BINARY_DIR}/bin/chip_config_xilinx.txt COPYONLY)
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configure_file(reset_chip_xilinx.txt ${CMAKE_BINARY_DIR}/bin/reset_chip_xilinx.txt COPYONLY)
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configure_file(enable_clock_pattern.pyat ${CMAKE_BINARY_DIR}/bin/enable_clock_pattern.pyat COPYONLY)
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configure_file(readout_pattern.pyat ${CMAKE_BINARY_DIR}/bin/readout_pattern.pyat COPYONLY)
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@ -48,6 +48,10 @@ $(PROGS): $(OBJS)
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mkdir -p $(DESTDIR)
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$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
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mv $(PROGS) $(DESTDIR)
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cp chip_config_xilinx.txt $(DESTDIR)
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cp reset_chip_xilinx.txt $(DESTDIR)
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cp enable_clock_pattern.pyat $(DESTDIR)
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cp readout_pattern.pyat $(DESTDIR)
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rm $(main_src)*.o $(md5_dir)*.o
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clean:
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rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb $(main_src)*.o $(md5_dir)*.o
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@ -17,12 +17,24 @@
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#define EMPTY4REG (0x4)
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#define STATUSREG1 (0x8)
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#define STATUS_REG (0x8)
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#define TRANSMISSIONBUSY_OFST (0)
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#define TRANSMISSIONBUSY_MSK (0x00000001 << TRANSMISSIONBUSY_OFST)
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#define PATTERN_RUNNING_OFST (0)
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#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
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#define RX_BUSY_OFST (1)
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#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
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#define PROCESSING_BUSY_OFST (2)
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#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
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#define UDP_GEN_BUSY_OFST (3)
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#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
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#define NETWORK_BUSY_OFST (4)
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#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
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#define WAIT_FOR_TRIGGER_OFST (5)
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#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST)
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#define RX_NOT_GOOD_OFST (6)
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#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
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#define STATUSREG2 (0xC)
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#define STATUS_REG2 (0xC)
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#define FPGAVERSIONREG (0x10)
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@ -31,7 +43,7 @@
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#define FPGADETTYPE_OFST (24)
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#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
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#define EMPTY14REG (0x14)
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#define FPGA_GIT_HEAD (0x14)
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#define FIXEDPATTERNREG (0x18)
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#define FIXEDPATTERNVAL (0xACDC2016)
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@ -889,7 +901,10 @@
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#define GTTPOWERGOOD_OFST (26)
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#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
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#define EMPTY654REG (0x654)
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#define TRANSCEIVERSTATUS2 (0x654)
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#define RXLOCKED_OFST (0)
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#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
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#define TRANSCEIVERCONTROL (0x658)
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@ -905,30 +920,58 @@
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#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
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#define RXPOLARITY_OFST (5)
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#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
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#define RXERRORCNTRESET_OFST (9)
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#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
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#define RXMSBLSBINVERT_OFST (13)
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#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
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#define EMPTY65CREG (0x65C)
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#define TRANSCEIVERERRCNT_REG0 (0x65C)
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#define EMPTY660REG (0x660)
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#define TRANSCEIVERERRCNT_REG1 (0x660)
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#define EMPTY664REG (0x664)
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#define TRANSCEIVERERRCNT_REG2 (0x664)
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#define EMPTY668REG (0x668)
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#define TRANSCEIVERERRCNT_REG3 (0x668)
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#define EMPTY66CREG (0x66C)
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#define TRANSCEIVERALIGNCNT_REG0 (0x66C)
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#define EMPTY670REG (0x670)
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#define RXALIGNCNTCH0_OFST (0)
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#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
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#define EMPTY674REG (0x674)
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#define TRANSCEIVERALIGNCNT_REG1 (0x670)
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#define EMPTY678REG (0x678)
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#define RXALIGNCNTCH1_OFST (0)
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#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
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#define EMPTY67CREG (0x67C)
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#define TRANSCEIVERALIGNCNT_REG2 (0x674)
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#define EMPTY680REG (0x680)
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#define RXALIGNCNTCH2_OFST (0)
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#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
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#define EMPTY684REG (0x684)
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#define TRANSCEIVERALIGNCNT_REG3 (0x678)
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#define EMPTY688REG (0x688)
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#define RXALIGNCNTCH3_OFST (0)
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#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
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#define TRANSCEIVERLASTWORD_REG0 (0x67C)
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#define RXDATACH0_OFST (0)
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#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
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#define TRANSCEIVERLASTWORD_REG1 (0x680)
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#define RXDATACH1_OFST (0)
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#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
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#define TRANSCEIVERLASTWORD_REG2 (0x684)
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#define RXDATACH2_OFST (0)
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#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
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#define TRANSCEIVERLASTWORD_REG3 (0x688)
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#define RXDATACH3_OFST (0)
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#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
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#define EMPTY68CREG (0x68C)
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Binary file not shown.
@ -0,0 +1,24 @@
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# Prepare MH02 configuration
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reg 0x600 0x00000041
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reg 0x604 0x01200004
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# configure Matterhorn SPI
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setbit 0x608 0
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# wait till config is done
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pollbit 0x608 3 0
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# reset transceiver
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reg 0x658 0x0
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reg 0x658 0x1
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reg 0x658 0x0
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# set MSB LSB inversions and polarity for transceiver
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reg 0x658 0x61e0
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# Enable MH02 PLL clock
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patternX enable_clock_pattern.pyat
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# start the flow
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setbit 0x108 0
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clearbit 0x108 0
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sleep 1
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@ -0,0 +1,8 @@
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patword 0x0000 0x0000000000000000
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patword 0x0001 0x0000000000008000
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patword 0x0002 0x0000000000008000
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patword 0x0003 0x0000000000008000
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patword 0x0004 0x0000000000008000
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patword 0x0005 0x0000000000008000
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patioctrl 0x01b3ffff
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patlimits 0x0000 0x0005
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@ -0,0 +1,22 @@
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patword 0x0000 0x0000000000008000
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patword 0x0001 0x0000000000008000
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patword 0x0002 0x0000000000008000
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patword 0x0003 0x0000000000008000
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patword 0x0004 0x0000000000008000
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patword 0x0005 0x0000000000008000
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patword 0x0006 0x0000000000008000
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patword 0x0007 0x0000000000008000
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patword 0x0008 0x0000000000008000
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patword 0x0009 0x0000000000008000
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patword 0x000a 0x0000000000008000
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patword 0x000b 0x0000000000108000
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patword 0x000c 0x0000000000108000
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patword 0x000d 0x0000000000108000
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patword 0x000e 0x0000000000108000
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patword 0x000f 0x0000000000008000
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patword 0x0010 0x0000000000008000
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patword 0x0011 0x0000000000008000
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patword 0x0012 0x0000000000008000
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patword 0x0013 0x0000000000008000
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patioctrl 0x01b3ffff
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patlimits 0x0000 0x0013
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@ -0,0 +1,40 @@
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# turn off clock
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setbit 0x600 16
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setbit 0x608 0
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sleep 1
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# reset Matterhorn periphery
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setbit 0x608 1
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sleep 1
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# turn on clock
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clearbit 0x600 16
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setbit 0x608 0
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sleep 1
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# reset rx transceiver datapath
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setbit 0x658 4
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sleep 1
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# reset 8b10b counters
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setbit 0x658 9
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setbit 0x658 10
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setbit 0x658 11
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setbit 0x658 12
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sleep 1
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clearbit 0x658 9
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clearbit 0x658 10
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# reset buffer fifos
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reg 0x5C8 0xFFFFFFFF
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reg 0x5D0 0xFFFFFFFF
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reg 0x5D8 0xFFFFFFFF
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reg 0x5C8 0x0
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reg 0x5D0 0x0
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reg 0x5D8 0x0
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setbit 0x500 18
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# load default pattern
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patternX readout_pattern.pyat
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@ -492,7 +492,16 @@ void setTransceiverAlignment(int align) {
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#endif
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int isTransceiverAligned() {
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return (bus_r(TRANSCEIVERSTATUS) & RXBYTEISALIGNED_MSK);
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int times = 0;
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int retval = bus_r(TRANSCEIVERSTATUS2) & RXLOCKED_MSK;
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while (retval) {
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retval = bus_r(TRANSCEIVERSTATUS2) & RXLOCKED_MSK;
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times++;
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usleep(10);
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if (times == 5)
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return 1;
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}
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return retval;
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}
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int waitTransceiverAligned(char *mess) {
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@ -511,7 +520,9 @@ int waitTransceiverAligned(char *mess) {
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int times = 0;
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while (transceiverWordAligned == 0) {
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if (times++ > WAIT_TIME_OUT_0US_TIMES) {
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sprintf(mess, "Transceiver alignment timed out\n");
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sprintf(mess, "Transceiver alignment timed out. Check connection, "
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"p-n inversions, LSB-MSB inversions, link error "
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"counters and channel enable settings\n");
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LOG(logERROR, (mess));
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return FAIL;
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}
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@ -587,34 +598,197 @@ int getPowerChip() {
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int configureChip(char *mess) {
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LOG(logINFOBLUE, ("\tConfiguring chip\n"));
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// enable correct endianness (Only for MH_PR_2)
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// uint32_t addr = MATTERHORNSPIREG1;
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// bus_w(addr, bus_r(addr) &~MATTERHORNSPI1_MSK);
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// bus_w(addr, bus_r(addr) | ((0x40000 << MATTERHORNSPI1_OFST) &
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// MATTERHORNSPI1_MSK));
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// start configuration
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uint32_t addr = MATTERHORNSPICTRL;
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bus_w(addr, bus_r(addr) | CONFIGSTART_P_MSK);
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bus_w(addr, bus_r(addr) & ~CONFIGSTART_P_MSK);
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// wait until configuration is done
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#ifndef VIRTUAL
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int configDone = (bus_r(MATTERHORNSPICTRL) & BUSY_MSK);
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int times = 0;
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while (configDone == 0) {
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if (times++ > WAIT_TIME_OUT_0US_TIMES) {
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sprintf(mess, "Configuration of chip timed out\n");
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LOG(logERROR, (mess));
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return FAIL;
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}
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usleep(0);
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configDone = (bus_r(MATTERHORNSPICTRL) & BUSY_MSK);
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chipConfigured = 0;
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if (readConfigFile(mess, CONFIG_CHIP_FILE, "chip config") == FAIL) {
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return FAIL;
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}
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#endif
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if (readConfigFile(mess, RESET_CHIP_FILE, "reset chip") == FAIL) {
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return FAIL;
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}
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LOG(logINFOBLUE, ("Chip configured.\n"));
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chipConfigured = 1;
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LOG(logINFOBLUE, ("\tChip configured\n"));
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return OK;
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}
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int readConfigFile(char *mess, char *fileName, char *fileType) {
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const int fileNameSize = 128;
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char fname[fileNameSize];
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if (getAbsPath(fname, fileNameSize, fileName) == FAIL) {
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sprintf(mess, "Could not get full path for %s file [%s].\n", fileType,
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fname);
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LOG(logERROR, (mess));
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return FAIL;
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}
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if (access(fname, F_OK) != 0) {
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sprintf(mess, "Could not find %s file [%s].\n", fileType, fname);
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LOG(logERROR, (mess));
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return FAIL;
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}
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FILE *fd = fopen(fname, "r");
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if (fd == NULL) {
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sprintf(mess, "Could not open on-board detector server %s file [%s].\n",
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fileType, fname);
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LOG(logERROR, (mess));
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return FAIL;
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}
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LOG(logINFOBLUE, ("Reading %s file %s\n", fileType, fname));
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const size_t LZ = 256;
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char line[LZ];
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memset(line, 0, LZ);
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char command[LZ];
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||||
// keep reading a line
|
||||
while (fgets(line, LZ, fd)) {
|
||||
|
||||
// ignore comments
|
||||
if (line[0] == '#') {
|
||||
LOG(logDEBUG1, ("Ignoring Comment\n"));
|
||||
continue;
|
||||
}
|
||||
|
||||
// ignore empty lines
|
||||
if (strlen(line) <= 1) {
|
||||
LOG(logDEBUG1, ("Ignoring Empty line\n"));
|
||||
continue;
|
||||
}
|
||||
|
||||
// removing leading spaces
|
||||
if (line[0] == ' ' || line[0] == '\t') {
|
||||
int len = strlen(line);
|
||||
// find first valid character
|
||||
int i = 0;
|
||||
for (i = 0; i < len; ++i) {
|
||||
if (line[i] != ' ' && line[i] != '\t') {
|
||||
break;
|
||||
}
|
||||
}
|
||||
// ignore the line full of spaces (last char \n)
|
||||
if (i >= len - 1) {
|
||||
LOG(logDEBUG1, ("Ignoring line full of spaces\n"));
|
||||
continue;
|
||||
}
|
||||
// copying only valid char
|
||||
char temp[LZ];
|
||||
memset(temp, 0, LZ);
|
||||
memcpy(temp, line + i, strlen(line) - i);
|
||||
memset(line, 0, LZ);
|
||||
memcpy(line, temp, strlen(temp));
|
||||
LOG(logDEBUG1, ("Removing leading spaces.\n"));
|
||||
}
|
||||
|
||||
LOG(logDEBUG1, ("Command to process: (size:%d) %.*s\n", strlen(line),
|
||||
strlen(line) - 1, line));
|
||||
memset(command, 0, LZ);
|
||||
|
||||
// reg command
|
||||
if (!strncmp(line, "reg", strlen("reg"))) {
|
||||
uint32_t addr = 0;
|
||||
uint32_t val = 0;
|
||||
if (sscanf(line, "%s %x %x", command, &addr, &val) != 3) {
|
||||
sprintf(mess, "Could not scan reg command. Line:[%s].\n", line);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
bus_w(addr, val);
|
||||
LOG(logINFOBLUE, ("Wrote 0x%x to 0x%x\n", val, addr));
|
||||
}
|
||||
|
||||
// setbit command
|
||||
else if (!strncmp(line, "setbit", strlen("setbit"))) {
|
||||
uint32_t addr = 0;
|
||||
uint32_t bit = 0;
|
||||
if (sscanf(line, "%s %x %d", command, &addr, &bit) != 3) {
|
||||
sprintf(mess, "Could not scan setbit command. Line:[%s].\n",
|
||||
line);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
bus_w(addr, bus_r(addr) | (1 << bit));
|
||||
LOG(logINFOBLUE, ("Set bit %d in 0x%x\n", bit, addr));
|
||||
}
|
||||
|
||||
// clearbit command
|
||||
else if (!strncmp(line, "clearbit", strlen("clearbit"))) {
|
||||
uint32_t addr = 0;
|
||||
uint32_t bit = 0;
|
||||
if (sscanf(line, "%s %x %d", command, &addr, &bit) != 3) {
|
||||
sprintf(mess, "Could not scan clearbit command. Line:[%s].\n",
|
||||
line);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
bus_w(addr, bus_r(addr) & ~(1 << bit));
|
||||
LOG(logINFOBLUE, ("Cleared bit %d in 0x%x\n", bit, addr));
|
||||
}
|
||||
|
||||
// pollbit command
|
||||
else if (!strncmp(line, "pollbit", strlen("pollbit"))) {
|
||||
uint32_t addr = 0;
|
||||
uint32_t bit = 0;
|
||||
uint32_t val = 0;
|
||||
if (sscanf(line, "%s %x %d %d", command, &addr, &bit, &val) != 4) {
|
||||
sprintf(mess, "Could not scan pollbit command. Line:[%s].\n",
|
||||
line);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
#ifndef VIRTUAL
|
||||
int times = 0;
|
||||
while (((bus_r(addr) >> bit) & 0x1) != val) {
|
||||
if (times++ > WAIT_TIME_OUT_0US_TIMES) {
|
||||
sprintf(mess, "Polling bit %d in 0x%x timed out\n", bit,
|
||||
addr);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
usleep(0);
|
||||
}
|
||||
#endif
|
||||
LOG(logINFOBLUE, ("Polled bit %d in 0x%x\n", bit, addr));
|
||||
}
|
||||
|
||||
// patternX command
|
||||
else if (!strncmp(line, "patternX", strlen("patternX"))) {
|
||||
// take a file name and call loadPAtterFile
|
||||
char patternFileName[LZ];
|
||||
if (sscanf(line, "%s %s", command, patternFileName) != 2) {
|
||||
sprintf(mess, "Could not scan patternX command. Line:[%s].\n",
|
||||
line);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
if (loadPatternFile(patternFileName, mess) == FAIL) {
|
||||
return FAIL;
|
||||
}
|
||||
LOG(logINFOBLUE, ("loaded pattern [%s].\n", patternFileName));
|
||||
}
|
||||
|
||||
// sleep command
|
||||
else if (!strncmp(line, "sleep", strlen("sleep"))) {
|
||||
int time = 0;
|
||||
if (sscanf(line, "%s %d", command, &time) != 2) {
|
||||
sprintf(mess, "Could not scan sleep command. Line:[%s].\n",
|
||||
line);
|
||||
LOG(logERROR, (mess));
|
||||
return FAIL;
|
||||
}
|
||||
usleep(time * 1000 * 1000);
|
||||
LOG(logINFOBLUE, ("Slept for %d s\n", time));
|
||||
}
|
||||
|
||||
// other commands
|
||||
else {
|
||||
sprintf(mess,
|
||||
"Could not scan command from on-board server "
|
||||
"%s file. Line:[%s].\n",
|
||||
fileType, line);
|
||||
break;
|
||||
}
|
||||
memset(line, 0, LZ);
|
||||
}
|
||||
fclose(fd);
|
||||
LOG(logINFOBLUE, ("Successfully read %s file.\n", fileType));
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1328,31 +1502,13 @@ int startStateMachine() {
|
||||
return OK;
|
||||
#endif
|
||||
|
||||
LOG(logINFOBLUE, ("Starting State Machine\n"));
|
||||
// cleanFifos(); removing this for now as its done before readout pattern
|
||||
LOG(logINFOBLUE, ("Starting readout\n"));
|
||||
|
||||
// start state machine
|
||||
bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
|
||||
|
||||
LOG(logINFORED, ("Waiting for exposing to be done\n"));
|
||||
int exposingDone = (bus_r(FLOW_STATUS_REG) & RSM_BUSY_MSK);
|
||||
while (exposingDone != 0) {
|
||||
usleep(0);
|
||||
exposingDone = (bus_r(FLOW_STATUS_REG) & RSM_BUSY_MSK);
|
||||
}
|
||||
|
||||
LOG(logINFORED, ("Starting readout of chip to fifo\n"));
|
||||
// MM:readout via pattern does not work right now due to firmware bug,
|
||||
// readout via MatterhornCTRL for the moment
|
||||
// bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
|
||||
bus_w(MATTERHORNSPICTRL, bus_r(MATTERHORNSPICTRL) | STARTREAD_P_MSK);
|
||||
|
||||
LOG(logINFORED, ("Waiting until k-words or end of acquisition\n"));
|
||||
usleep(0);
|
||||
int commaDet = (bus_r(TRANSCEIVERSTATUS) & RXCOMMADET_MSK);
|
||||
while (commaDet == 0) {
|
||||
usleep(0);
|
||||
commaDet = (bus_r(TRANSCEIVERSTATUS) & RXCOMMADET_MSK);
|
||||
}
|
||||
LOG(logINFORED, ("Kwords or end of acquisition detected\n"));
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1467,56 +1623,6 @@ int stopStateMachine() {
|
||||
return OK;
|
||||
}
|
||||
|
||||
int startReadOut() {
|
||||
LOG(logINFOBLUE, ("Starting Readout\n"));
|
||||
#ifdef VIRTUAL
|
||||
// cannot set #frames and exptiem temporarily to 1 and 0,
|
||||
// because have to set it back after readout (but this is non blocking)
|
||||
return startStateMachine();
|
||||
#endif
|
||||
// check if data in fifo
|
||||
int ret = FAIL;
|
||||
if (transceiverEnable) {
|
||||
if ((bus_r(X_FIFO_EMPTY_STATUS_REG) & X_FIFO_EMPTY_STATUS_MSK) !=
|
||||
X_FIFO_EMPTY_STATUS_MSK) {
|
||||
LOG(logINFO, ("Data in transceiver fifo\n"));
|
||||
ret = OK;
|
||||
}
|
||||
}
|
||||
if (analogEnable) {
|
||||
if (bus_r(A_FIFO_EMPTY_STATUS_REG) != BIT32_MSK) {
|
||||
LOG(logINFO, ("Data in analog fifo\n"));
|
||||
ret = OK;
|
||||
}
|
||||
}
|
||||
if (digitalEnable) {
|
||||
if ((bus_r(D_FIFO_EMPTY_STATUS_REG) & D_FIFO_EMPTY_STATUS_MSK) !=
|
||||
D_FIFO_EMPTY_STATUS_MSK) {
|
||||
LOG(logINFO, ("Data in digital fifo\n"));
|
||||
ret = OK;
|
||||
}
|
||||
}
|
||||
// if no module, dont check fifo empty
|
||||
if (checkModuleFlag && ret == FAIL) {
|
||||
LOG(logERROR, ("No data in fifo\n"));
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
LOG(logINFOBLUE, ("Streaming data from fifo\n"));
|
||||
bus_w(FIFO_TO_GB_CONTROL_REG,
|
||||
bus_r(FIFO_TO_GB_CONTROL_REG) | START_STREAMING_P_MSK);
|
||||
|
||||
// wait until streaming is done (not same as fifo empty)
|
||||
int streamingBusy = (bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK);
|
||||
while (streamingBusy != 0) {
|
||||
usleep(0);
|
||||
streamingBusy = (bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK);
|
||||
}
|
||||
LOG(logINFORED, ("Streaming done\n"));
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
int softwareTrigger() {
|
||||
#ifndef VIRTUAL
|
||||
// ready for trigger
|
||||
@ -1552,36 +1658,33 @@ enum runStatus getRunStatus() {
|
||||
LOG(logINFOBLUE, ("Status: IDLE\n"));
|
||||
return IDLE;
|
||||
#endif
|
||||
uint32_t retval = bus_r(FLOW_STATUS_REG);
|
||||
LOG(logINFO, ("Flow Status Register: %08x\n", retval));
|
||||
uint32_t retval = bus_r(STATUS_REG);
|
||||
LOG(logINFO, ("Status Register: %08x\n", retval));
|
||||
|
||||
if (retval & RSM_TRG_WAIT_MSK) {
|
||||
LOG(logINFOBLUE, ("Status: WAITING\n"));
|
||||
return WAITING;
|
||||
} else if (retval & RSM_BUSY_MSK) {
|
||||
LOG(logINFOBLUE, ("Status: RUNNING (exposing)\n"));
|
||||
return RUNNING;
|
||||
} else if (bus_r(MATTERHORNSPICTRL) & READOUTFROMASIC_MSK) {
|
||||
LOG(logINFOBLUE, ("Status: RUNNING (data from chip to fifo)\n"));
|
||||
return RUNNING;
|
||||
} else if (bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK) {
|
||||
LOG(logINFOBLUE, ("Status: TRANSMITTING\n"));
|
||||
return TRANSMITTING;
|
||||
if (retval == 0x0) {
|
||||
return IDLE;
|
||||
}
|
||||
|
||||
LOG(logINFOBLUE, ("Status: IDLE\n"));
|
||||
return IDLE;
|
||||
// TODO: STOPPED, ERROR?
|
||||
if (retval & RX_NOT_GOOD_MSK) {
|
||||
LOG(logINFOBLUE, ("Status: ERROR\n"));
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
if (retval & WAIT_FOR_TRIGGER_MSK) {
|
||||
LOG(logINFOBLUE, ("Status: WAITING\n"));
|
||||
return WAITING;
|
||||
}
|
||||
|
||||
LOG(logINFOBLUE, ("Status: RUNNING\n"));
|
||||
return RUNNING;
|
||||
// TODO: STOPPED?
|
||||
}
|
||||
|
||||
u_int32_t runBusy() {
|
||||
#ifdef VIRTUAL
|
||||
return ((sharedMemory_getStatus() == RUNNING) ? 1 : 0);
|
||||
#endif
|
||||
uint32_t exposingBusy = bus_r(FLOW_STATUS_REG) & RSM_BUSY_MSK;
|
||||
uint32_t fillingFifoBusy = bus_r(MATTERHORNSPICTRL) & READOUTFROMASIC_MSK;
|
||||
uint32_t streamingBusy = bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK;
|
||||
return (exposingBusy || fillingFifoBusy || streamingBusy);
|
||||
return (bus_r(STATUS_REG));
|
||||
}
|
||||
|
||||
void waitForAcquisitionEnd() {
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
#include "RegisterDefs.h"
|
||||
#include "sls/sls_detector_defs.h"
|
||||
|
||||
#define REQRD_FRMWRE_VRSN (0x230710)
|
||||
#define REQRD_FRMWRE_VRSN (0x250203)
|
||||
#define KERNEL_DATE_VRSN "Wed Nov 29 17:32:14 CET 2023"
|
||||
|
||||
#define LINKED_SERVER_NAME "xilinx_ctbDetectorServer"
|
||||
@ -40,6 +40,9 @@
|
||||
#define SLOWADC_DRIVER_FILE_NAME CURRENT_BOARD_LINKS_FOLDER "/ai%d"
|
||||
#define TEMP_DRIVER_FILE_NAME DEVICE_TREE_DST "0/in_temp7_input"
|
||||
|
||||
#define CONFIG_CHIP_FILE "chip_config_xilinx.txt"
|
||||
#define RESET_CHIP_FILE "reset_chip_xilinx.txt"
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
#define APIEIGER "developer 0x241107"
|
||||
#define APILIB "developer 0x241122"
|
||||
#define APIRECEIVER "developer 0x241122"
|
||||
#define APIXILINXCTB "developer 0x250131"
|
||||
#define APICTB "developer 0x250131"
|
||||
#define APIMYTHEN3 "developer 0x250131"
|
||||
#define APIXILINXCTB "developer 0x250213"
|
||||
#define APIJUNGFRAU "developer 0x250218"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user