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Xilinxctb/update reg (#1084)

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* updated RegisterDefs.h from firmware update

* Revert "updated RegisterDefs.h from firmware update"

This reverts commit 64f1b2546e.

* updated registers and had it formatted

* Revert "updated registers and had it formatted"

This reverts commit 1641b705b0.

* udpated registers from firmware, reading config file in server (chip config, reset chip, enable_clock_pattern) specific for matterhorn,this is done when powering on chip, removed startreadout, fixed status register bits, updated firmware version

* fix for patioctrl allowed for zxilinx and adding readout pattern for scientists that like to push the acquire button

* fixing default enable clock and readout pattern for xilinx (patioctrl has to be 32 bit)

* Xilinxctb/first image (#1094)

* reduce xilinxCTB readout done checks to single register, increased clockEna pattern limits, clear FPGA FiFos and counters on powerchip, disable counters 1-3 in matterhorn configuration

* change print of xilinxctb server

* remove acquisition done check

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>

* binary xilinx in

* formatting

* added reset of udp buffer FIFO to xilinxCTB

---------

Co-authored-by: Martin Mueller <72937414+mmarti04@users.noreply.github.com>
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
This commit is contained in:
maliakal_d
2025-02-18 11:30:51 +01:00
committed by GitHub
parent e933a25453
commit 117637863d
14 changed files with 402 additions and 149 deletions
Download Patch File Download Diff File Expand all files Collapse all files

79
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
View File

@ -17,12 +17,24 @@
#define EMPTY4REG (0x4)
#define STATUSREG1 (0x8)
#define STATUS_REG (0x8)
#define TRANSMISSIONBUSY_OFST (0)
#define TRANSMISSIONBUSY_MSK (0x00000001 << TRANSMISSIONBUSY_OFST)
#define PATTERN_RUNNING_OFST (0)
#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST)
#define RX_BUSY_OFST (1)
#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST)
#define PROCESSING_BUSY_OFST (2)
#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST)
#define UDP_GEN_BUSY_OFST (3)
#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST)
#define NETWORK_BUSY_OFST (4)
#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST)
#define WAIT_FOR_TRIGGER_OFST (5)
#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST)
#define RX_NOT_GOOD_OFST (6)
#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST)
#define STATUSREG2 (0xC)
#define STATUS_REG2 (0xC)
#define FPGAVERSIONREG (0x10)
@ -31,7 +43,7 @@
#define FPGADETTYPE_OFST (24)
#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST)
#define EMPTY14REG (0x14)
#define FPGA_GIT_HEAD (0x14)
#define FIXEDPATTERNREG (0x18)
#define FIXEDPATTERNVAL (0xACDC2016)
@ -889,7 +901,10 @@
#define GTTPOWERGOOD_OFST (26)
#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST)
#define EMPTY654REG (0x654)
#define TRANSCEIVERSTATUS2 (0x654)
#define RXLOCKED_OFST (0)
#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST)
#define TRANSCEIVERCONTROL (0x658)
@ -905,30 +920,58 @@
#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST)
#define RXPOLARITY_OFST (5)
#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST)
#define RXERRORCNTRESET_OFST (9)
#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST)
#define RXMSBLSBINVERT_OFST (13)
#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST)
#define EMPTY65CREG (0x65C)
#define TRANSCEIVERERRCNT_REG0 (0x65C)
#define EMPTY660REG (0x660)
#define TRANSCEIVERERRCNT_REG1 (0x660)
#define EMPTY664REG (0x664)
#define TRANSCEIVERERRCNT_REG2 (0x664)
#define EMPTY668REG (0x668)
#define TRANSCEIVERERRCNT_REG3 (0x668)
#define EMPTY66CREG (0x66C)
#define TRANSCEIVERALIGNCNT_REG0 (0x66C)
#define EMPTY670REG (0x670)
#define RXALIGNCNTCH0_OFST (0)
#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST)
#define EMPTY674REG (0x674)
#define TRANSCEIVERALIGNCNT_REG1 (0x670)
#define EMPTY678REG (0x678)
#define RXALIGNCNTCH1_OFST (0)
#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST)
#define EMPTY67CREG (0x67C)
#define TRANSCEIVERALIGNCNT_REG2 (0x674)
#define EMPTY680REG (0x680)
#define RXALIGNCNTCH2_OFST (0)
#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST)
#define EMPTY684REG (0x684)
#define TRANSCEIVERALIGNCNT_REG3 (0x678)
#define EMPTY688REG (0x688)
#define RXALIGNCNTCH3_OFST (0)
#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST)
#define TRANSCEIVERLASTWORD_REG0 (0x67C)
#define RXDATACH0_OFST (0)
#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST)
#define TRANSCEIVERLASTWORD_REG1 (0x680)
#define RXDATACH1_OFST (0)
#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST)
#define TRANSCEIVERLASTWORD_REG2 (0x684)
#define RXDATACH2_OFST (0)
#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST)
#define TRANSCEIVERLASTWORD_REG3 (0x688)
#define RXDATACH3_OFST (0)
#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST)
#define EMPTY68CREG (0x68C)