diff --git a/slsDetectorServers/slsDetectorServer/include/XILINX_FMC.h b/slsDetectorServers/slsDetectorServer/include/XILINX_FMC.h new file mode 100644 index 000000000..9b173d4ef --- /dev/null +++ b/slsDetectorServers/slsDetectorServer/include/XILINX_FMC.h @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: LGPL-3.0-or-other +// Copyright (C) 2021 Contributors to the SLS Detector Package + +int XILINX_FMC_enable_all(char *error_message, int message_size); +int XILINX_FMC_disable_all(char *error_message, int message_size); \ No newline at end of file diff --git a/slsDetectorServers/slsDetectorServer/src/XILINX_FMC.c b/slsDetectorServers/slsDetectorServer/src/XILINX_FMC.c new file mode 100644 index 000000000..7b34a5c90 --- /dev/null +++ b/slsDetectorServers/slsDetectorServer/src/XILINX_FMC.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: LGPL-3.0-or-other +// Copyright (C) 2021 Contributors to the SLS Detector Package +#include "XILINX_FMC.h" +#include "arm64.h" +#include "clogger.h" +#include +#include +#include + +// clang-format off +#define FMC_BASE_PATH "/root/fmc/" +#define FMC_VADJ_EN "FMC_VADJ_EN" +#define FMCP_VADJ_EN "FMCP_VADJ_EN" +#define FMCP_3V3_EN "FMCP_3V3_EN" +#define FMC_3V3_EN "FMC_3V3_EN" +#define FMC_12V_EN "FMC_12V_EN" +#define FMCP_12V_EN "FMCP_12V_EN" + +static const char *fmc_files[] = { + FMC_VADJ_EN, + FMCP_VADJ_EN, + FMCP_3V3_EN, + FMC_3V3_EN, + FMC_12V_EN, + FMCP_12V_EN +}; +#define FMC_NUM_FILES (sizeof(fmc_files) / sizeof(fmc_files[0])) +// clang-format on + +int XILINX_FMC_enable_all(char *error_message, int message_size) { + LOG(logINFOBLUE, ("enable FMC power\n")); +#ifdef VIRTUAL + return; +#endif + char full_path[64]; + for (size_t i = 0; i < FMC_NUM_FILES; ++i) { + const char *file = fmc_files[i]; + snprintf(full_path, sizeof(full_path), "%s%s", FMC_BASE_PATH, file); + FILE *fp = fopen(full_path, "w"); + if (fp == NULL) { + snprintf(error_message, message_size, + "XILINX_FMC: Couuld not enable.\n"); + LOG(logERROR, (error_message)); + return 1; + } + + if (fprintf(fp, "1\n") != 2) { + snprintf(error_message, message_size, + "XILINX_FMC: Could not write enable.\n"); + LOG(logERROR, (error_message)); + return 1; + } + fclose(fp); + } + return 0; +} + +int XILINX_FMC_disable_all(char *error_message, int message_size) { + LOG(logINFOBLUE, ("disable FMC power\n")); +#ifdef VIRTUAL + return; +#endif + char full_path[64]; + for (size_t i = 0; i < FMC_NUM_FILES; ++i) { + const char *file = fmc_files[i]; + snprintf(full_path, sizeof(full_path), "%s%s", FMC_BASE_PATH, file); + FILE *fp = fopen(full_path, "w"); + if (fp == NULL) { + snprintf(error_message, message_size, + "XILINX_FMC: Could not disable\n"); + LOG(logERROR, (error_message)); + return 1; + } + if (fprintf(fp, "0\n") != 2) { + snprintf(error_message, message_size, + "XILINX_FMC: Could not write disable.\n"); + LOG(logERROR, (error_message)); + return 1; + } + fclose(fp); + } + return 0; +} \ No newline at end of file diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt b/slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt index fa72ff586..284c9b6fc 100644 --- a/slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt +++ b/slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt @@ -7,6 +7,7 @@ add_executable(xilinx_ctbDetectorServer_virtual ../slsDetectorServer/src/communication_funcs.c ../slsDetectorServer/src/arm64.c ../slsDetectorServer/src/XILINX_PLL.c + ../slsDetectorServer/src/XILINX_FMC.c ../slsDetectorServer/src/common.c ../slsDetectorServer/src/sharedMemory.c ../slsDetectorServer/src/loadPattern.c diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/Makefile b/slsDetectorServers/xilinx_ctbDetectorServer/Makefile index f08ac3792..487959d6f 100755 --- a/slsDetectorServers/xilinx_ctbDetectorServer/Makefile +++ b/slsDetectorServers/xilinx_ctbDetectorServer/Makefile @@ -23,7 +23,7 @@ DESTDIR ?= bin INSTMODE = 0777 SRCS = slsDetectorFunctionList.c -SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)XILINX_PLL.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c +SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)arm64.c $(main_src)XILINX_PLL.c $(main_src)XILINX_FMC.c $(main_src)common.c $(main_src)/sharedMemory.c $(main_src)/loadPattern.c $(md5_dir)md5.c $(main_src)programViaArm.c $(main_src)LTC2620_Driver.c OBJS = $(SRCS:.c=.o) diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h b/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h index 4d5563e45..1ff521b05 100644 --- a/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h +++ b/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h @@ -7,450 +7,699 @@ #define REG_OFFSET (4) #define PATTERN_STEP0_MSB_REG (0x10004) #define PATTERN_STEP0_LSB_REG (0x10000) - -#define CTRL_REG (0x8000) - -#define POWER_VIO_OFST (0) -#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST) -#define POWER_VCC_A_OFST (1) -#define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST) -#define POWER_VCC_B_OFST (2) -#define POWER_VCC_B_MSK (0x00000001 << POWER_VCC_B_OFST) -#define POWER_VCC_C_OFST (3) -#define POWER_VCC_C_MSK (0x00000001 << POWER_VCC_C_OFST) -#define POWER_VCC_D_OFST (4) -#define POWER_VCC_D_MSK (0x00000001 << POWER_VCC_D_OFST) - -#define STATUS_REG (0x8004) - -#define PATTERN_RUNNING_OFST (0) -#define PATTERN_RUNNING_MSK (0x00000001 << PATTERN_RUNNING_OFST) -#define RX_BUSY_OFST (1) -#define RX_BUSY_MSK (0x00000001 << RX_BUSY_OFST) -#define PROCESSING_BUSY_OFST (2) -#define PROCESSING_BUSY_MSK (0x00000001 << PROCESSING_BUSY_OFST) -#define UDP_GEN_BUSY_OFST (3) -#define UDP_GEN_BUSY_MSK (0x00000001 << UDP_GEN_BUSY_OFST) -#define NETWORK_BUSY_OFST (4) -#define NETWORK_BUSY_MSK (0x00000001 << NETWORK_BUSY_OFST) -#define WAIT_FOR_TRIGGER_OFST (5) -#define WAIT_FOR_TRIGGER_MSK (0x00000001 << WAIT_FOR_TRIGGER_OFST) -#define RX_NOT_GOOD_OFST (6) -#define RX_NOT_GOOD_MSK (0x00000001 << RX_NOT_GOOD_OFST) - -#define STATUS_REG2 (0x8008) - -#define FPGAVERSIONREG (0x800C) - -#define FPGACOMPDATE_OFST (0) -#define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST) -#define FPGADETTYPE_OFST (24) -#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST) - -#define FPGA_GIT_HEAD (0x8010) - -#define FIXEDPATTERNREG (0x8014) -#define FIXEDPATTERNVAL (0xACDC2016) - -#define APIVERSIONREG (0x8018) - -#define APICOMPDATE_OFST (0) -#define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST) -#define APIDETTYPE_OFST (24) -#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST) - -#define A_FIFO_OVERFLOW_STATUS_REG (0x9000) - -#define A_FIFO_EMPTY_STATUS_REG (0x9004) - -#define A_FIFO_FULL_STATUS_REG (0x9008) - -#define D_FIFO_OVERFLOW_STATUS_REG (0x900C) - -#define D_FIFO_OVERFLOW_STATUS_OFST (0) -#define D_FIFO_OVERFLOW_STATUS_MSK (0x00000001 << D_FIFO_OVERFLOW_STATUS_OFST) - -#define D_FIFO_EMPTY_STATUS_REG (0x9010) - -#define D_FIFO_EMPTY_STATUS_OFST (0) -#define D_FIFO_EMPTY_STATUS_MSK (0x00000001 << D_FIFO_EMPTY_STATUS_OFST) - -#define D_FIFO_FULL_STATUS_REG (0x9014) - -#define D_FIFO_FULL_STATUS_OFST (0) -#define D_FIFO_FULL_STATUS_MSK (0x00000001 << D_FIFO_FULL_STATUS_OFST) - -#define X_FIFO_OVERFLOW_STATUS_REG (0x9018) - -#define X_FIFO_OVERFLOW_STATUS_OFST (0) -#define X_FIFO_OVERFLOW_STATUS_MSK (0x0000000f << X_FIFO_OVERFLOW_STATUS_OFST) - -#define X_FIFO_EMPTY_STATUS_REG (0x901C) - -#define X_FIFO_EMPTY_STATUS_OFST (0) -#define X_FIFO_EMPTY_STATUS_MSK (0x0000000f << X_FIFO_EMPTY_STATUS_OFST) - -#define X_FIFO_FULL_STATUS_REG (0x9020) - -#define X_FIFO_FULL_STATUS_OFST (0) -#define X_FIFO_FULL_STATUS_MSK (0x0000000f << X_FIFO_FULL_STATUS_OFST) - -#define A_FIFO_CLEAN_REG (0x9024) - -#define D_FIFO_CLEAN_REG (0x9028) - -#define D_FIFO_CLEAN_OFST (0) -#define D_FIFO_CLEAN_MSK (0x00000001 << D_FIFO_CLEAN_OFST) - -#define X_FIFO_CLEAN_REG (0x902C) - -#define X_FIFO_CLEAN_OFST (0) -#define X_FIFO_CLEAN_MSK (0x0000000f << X_FIFO_CLEAN_OFST) - -#define FIFO_TO_GB_CONTROL_REG (0xA000) - -#define ENABLED_CHANNELS_ADC_OFST (0) -#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST) -#define ENABLED_CHANNELS_D_OFST (8) -#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST) -#define ENABLED_CHANNELS_X_OFST (9) -#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST) -#define RO_MODE_ADC_OFST (13) -#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST) -#define RO_MODE_D_OFST (14) -#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST) -#define RO_MODE_X_OFST (15) -#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST) -#define COUNT_FRAMES_FROM_UPDATE_OFST (16) -#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST) -#define START_STREAMING_P_OFST (17) -#define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST) -#define STREAM_BUFFER_CLEAR_OFST (18) -#define STREAM_BUFFER_CLEAR_MSK (0x00000001 << STREAM_BUFFER_CLEAR_OFST) - -#define NO_SAMPLES_D_REG (0xA004) - -#define NO_SAMPLES_D_OFST (0) -#define NO_SAMPLES_D_MSK (0x00003fff << NO_SAMPLES_D_OFST) - -#define NO_SAMPLES_A_REG (0xA008) - -#define NO_SAMPLES_A_OFST (0) -#define NO_SAMPLES_A_MSK (0x00003fff << NO_SAMPLES_A_OFST) - -#define NO_SAMPLES_X_REG (0xA00C) - -#define NO_SAMPLES_X_OFST (0) -#define NO_SAMPLES_X_MSK (0x00001fff << NO_SAMPLES_X_OFST) - -#define COUNT_FRAMES_FROM_REG_1 (0xA010) - -#define COUNT_FRAMES_FROM_REG_2 (0xA014) - -#define LOCAL_FRAME_NUMBER_REG_1 (0xA018) - -#define LOCAL_FRAME_NUMBER_REG_2 (0xA01C) - -#define PKTPACKETLENGTHREG (0xA020) - -#define PACKETLENGTH1G_OFST (0) -#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST) -#define PACKETLENGTH10G_OFST (16) -#define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST) - -#define PKTNOPACKETSREG (0xA024) - -#define NOPACKETS1G_OFST (0) -#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST) -#define NOPACKETS10G_OFST (16) -#define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST) - -#define PKTCTRLREG (0xA028) - -#define NOSERVERS_OFST (0) -#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST) -#define SERVERSTART_OFST (8) -#define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST) -#define ETHINTERF_OFST (16) -#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST) - -#define PKTCOORDREG1 (0xA02C) - -#define COORDX_OFST (0) -#define COORDX_MSK (0x0000ffff << COORDX_OFST) -#define COORDY_OFST (16) -#define COORDY_MSK (0x0000ffff << COORDY_OFST) - -#define PKTCOORDREG2 (0xA030) - -#define COORDZ_OFST (0) -#define COORDZ_MSK (0x0000ffff << COORDZ_OFST) - -#define PATTERN_OUT_LSB_REG (0xB000) - -#define PATTERN_OUT_MSB_REG (0xB004) - -#define PATTERN_IN_LSB_REG (0xB008) - -#define PATTERN_IN_MSB_REG (0xB00C) - -#define PATTERN_MASK_LSB_REG (0xB010) - -#define PATTERN_MASK_MSB_REG (0xB014) - -#define PATTERN_SET_LSB_REG (0xB018) - -#define PATTERN_SET_MSB_REG (0xB01C) - -#define PATTERN_CNTRL_REG (0xB020) - -#define PATTERN_CNTRL_WR_OFST (0) -#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST) -#define PATTERN_CNTRL_RD_OFST (1) -#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST) -#define PATTERN_CNTRL_ADDR_OFST (16) -#define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST) - -#define PATTERN_LIMIT_REG (0xB024) - -#define PATTERN_LIMIT_STRT_OFST (0) -#define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST) -#define PATTERN_LIMIT_STP_OFST (16) -#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST) - -#define PATTERN_IO_CNTRL_LSB_REG (0xB028) - -#define PATTERN_IO_CNTRL_MSB_REG (0xB02C) - -#define FLOW_CONTROL_REG (0xB030) - -#define START_F_OFST (0) -#define START_F_MSK (0x00000001 << START_F_OFST) -#define STOP_F_OFST (1) -#define STOP_F_MSK (0x00000001 << STOP_F_OFST) -#define RST_F_OFST (2) -#define RST_F_MSK (0x00000001 << RST_F_OFST) -#define SW_TRIGGER_F_OFST (3) -#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST) -#define TRIGGER_ENABLE_OFST (4) -#define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST) -#define RSM_BUSY_OFST (5) -#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST) -#define RSM_TRG_WAIT_OFST (6) -#define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST) -#define CSM_BUSY_OFST (7) -#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST) - -#define DELAY_IN_REG_1 (0xB034) - -#define DELAY_IN_REG_2 (0xB038) - -#define CYCLES_IN_REG_1 (0xB03C) - -#define CYCLES_IN_REG_2 (0xB040) - -#define FRAMES_IN_REG_1 (0xB044) - -#define FRAMES_IN_REG_2 (0xB048) - -#define PERIOD_IN_REG_1 (0xB04C) - -#define PERIOD_IN_REG_2 (0xB050) - -#define PATTERN_TEST_REG (0xB054) - -#define PATTERN_FIRMWARE_REG (0xB058) - -#define PATTERN_WIDTH_OFST (0) -#define PATTERN_WIDTH_MSK (0x000000ff << PATTERN_WIDTH_OFST) -#define PATTERN_ADDR_WIDTH_OFST (8) -#define PATTERN_ADDR_WIDTH_MSK (0x000000ff << PATTERN_ADDR_WIDTH_OFST) -#define PATTERN_NLOOPS_NWAITS_OFST (16) -#define PATTERN_NLOOPS_NWAITS_MSK (0x000000ff << PATTERN_NLOOPS_NWAITS_OFST) -#define DIRECT_PATTERN_RAM_OFST (24) -#define DIRECT_PATTERN_RAM_MSK (0x00000001 << DIRECT_PATTERN_RAM_OFST) - -#define TIME_FROM_START_OUT_REG_1 (0xB05C) - -#define TIME_FROM_START_OUT_REG_2 (0xB060) - -#define FRAMES_FROM_START_OUT_REG_1 (0xB064) - -#define FRAMES_FROM_START_OUT_REG_2 (0xB068) - -#define FRAME_TIME_OUT_REG_1 (0xB06C) - -#define FRAME_TIME_OUT_REG_2 (0xB070) - -#define PATTERN_LOOPDEF_BASE (0xB080) - -#define PATTERN_LOOP_ADDR_WORD_OFST (0) -#define PATTERN_LOOP_ADDR_WORD_MSK (0x00000001 << PATTERN_LOOP_ADDR_WORD_OFST) -#define PATTERN_LOOP_ITERATION_WORD_OFST (1) -#define PATTERN_LOOP_ITERATION_WORD_MSK (0x00000001 << PATTERN_LOOP_ITERATION_WORD_OFST) -#define PATTERN_WAIT_ADDR_WORD_OFST (2) -#define PATTERN_WAIT_ADDR_WORD_MSK (0x00000001 << PATTERN_WAIT_ADDR_WORD_OFST) -#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3) -#define PATTERN_WAIT_TIMER_LSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_LSB_WORD_OFST) -#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4) -#define PATTERN_WAIT_TIMER_MSB_WORD_MSK (0x00000001 << PATTERN_WAIT_TIMER_MSB_WORD_OFST) -#define PATTERN_LOOPDEF_NWORDS_OFST (5) -#define PATTERN_LOOPDEF_NWORDS_MSK (0x00000001 << PATTERN_LOOPDEF_NWORDS_OFST) -#define PATTERN_WAIT_ADDR_OFST (0) -#define PATTERN_WAIT_ADDR_MSK (0x00001fff << PATTERN_WAIT_ADDR_OFST) -#define PATTERN_LOOP_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_ADDR_STRT_OFST) -#define PATTERN_LOOP_ADDR_STP_OFST (16) -#define PATTERN_LOOP_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_ADDR_STP_OFST) - -#define DBITFIFOCTRLREG (0xC000) - -#define DBITRD_OFST (0) -#define DBITRD_MSK (0x00000001 << DBITRD_OFST) -#define DBITRST_OFST (1) -#define DBITRST_MSK (0x00000001 << DBITRST_OFST) -#define DBITFULL_OFST (2) -#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST) -#define DBITEMPTY_OFST (3) -#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST) -#define DBITUNDERFLOW_OFST (4) -#define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST) -#define DBITOVERFLOW_OFST (5) -#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST) - -#define DBITFIFODATAREG1 (0xC004) - -#define DBITFIFODATAREG2 (0xC008) - -#define MATTERHORNSPIREG1 (0xC00C) - -#define MATTERHORNSPIREG2 (0xC010) - -#define MATTERHORNSPICTRL (0xC014) - -#define CONFIGSTART_P_OFST (0) -#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST) -#define PERIPHERYRST_P_OFST (1) -#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST) -#define STARTREAD_P_OFST (2) -#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST) -#define BUSY_OFST (3) -#define BUSY_MSK (0x00000001 << BUSY_OFST) -#define READOUTFROMASIC_OFST (4) -#define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST) - -#define TRANSCEIVERRXCTRL0REG1 (0xC100) - -#define TRANSCEIVERRXCTRL0REG2 (0xC104) - -#define TRANSCEIVERRXCTRL1REG1 (0xC108) - -#define TRANSCEIVERRXCTRL1REG2 (0xC10C) - -#define TRANSCEIVERRXCTRL2REG (0xC110) - -#define TRANSCEIVERRXCTRL3REG (0xC114) - -#define TRANSCEIVERSTATUS (0xC118) - -#define LINKDOWNLATCHEDOUT_OFST (0) -#define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST) -#define TXUSERCLKACTIVE_OFST (1) -#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST) -#define RXUSERCLKACTIVE_OFST (2) -#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST) -#define RXCOMMADET_OFST (3) -#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST) -#define RXBYTEREALIGN_OFST (7) -#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST) -#define RXBYTEISALIGNED_OFST (11) -#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST) -#define GTWIZRXCDRSTABLE_OFST (15) -#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST) -#define RESETTXDONE_OFST (16) -#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST) -#define RESETRXDONE_OFST (17) -#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST) -#define RXPMARESETDONE_OFST (18) -#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST) -#define TXPMARESETDONE_OFST (22) -#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST) -#define GTTPOWERGOOD_OFST (26) -#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST) - -#define TRANSCEIVERSTATUS2 (0xC11C) - -#define RXLOCKED_OFST (0) -#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST) - -#define TRANSCEIVERCONTROL (0xC120) - -#define GTWIZRESETALL_OFST (0) -#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST) -#define RESETTXPLLANDDATAPATH_OFST (1) -#define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST) -#define RESETTXDATAPATHIN_OFST (2) -#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST) -#define RESETRXPLLANDDATAPATH_OFST (3) -#define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST) -#define RESETRXDATAPATHIN_OFST (4) -#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST) -#define RXPOLARITY_OFST (5) -#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST) -#define RXERRORCNTRESET_OFST (9) -#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST) -#define RXMSBLSBINVERT_OFST (13) -#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST) - -#define TRANSCEIVERERRCNT_REG0 (0xC124) - -#define TRANSCEIVERERRCNT_REG1 (0xC128) - -#define TRANSCEIVERERRCNT_REG2 (0xC12C) - -#define TRANSCEIVERERRCNT_REG3 (0xC130) - -#define TRANSCEIVERALIGNCNT_REG0 (0xC134) - -#define RXALIGNCNTCH0_OFST (0) -#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST) - -#define TRANSCEIVERALIGNCNT_REG1 (0xC138) - -#define RXALIGNCNTCH1_OFST (0) -#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST) - -#define TRANSCEIVERALIGNCNT_REG2 (0xC13C) - -#define RXALIGNCNTCH2_OFST (0) -#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST) - -#define TRANSCEIVERALIGNCNT_REG3 (0xC140) - -#define RXALIGNCNTCH3_OFST (0) -#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST) - -#define TRANSCEIVERLASTWORD_REG0 (0xC144) - -#define RXDATACH0_OFST (0) -#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST) - -#define TRANSCEIVERLASTWORD_REG1 (0xC148) - -#define RXDATACH1_OFST (0) -#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST) - -#define TRANSCEIVERLASTWORD_REG2 (0xC14C) - -#define RXDATACH2_OFST (0) -#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST) - -#define TRANSCEIVERLASTWORD_REG3 (0xC150) - -#define RXDATACH3_OFST (0) -#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST) - - +#ifndef __CHEBY__XCTB__H__ +#define __CHEBY__XCTB__H__ + +#define XCTB_SIZE 49924 /* 0xc304 */ + +/* REG CTRL_Reg */ +#define CTRL_REG 0x8000UL +#define POWER_VIO 0x1UL +#define POWER_VIO_MSK 0x1UL +#define POWER_VIO_OFST 0 +#define POWER_VCC_A 0x2UL +#define POWER_VCC_A_MSK 0x2UL +#define POWER_VCC_A_OFST 1 +#define POWER_VCC_B 0x4UL +#define POWER_VCC_B_MSK 0x4UL +#define POWER_VCC_B_OFST 2 +#define POWER_VCC_C 0x8UL +#define POWER_VCC_C_MSK 0x8UL +#define POWER_VCC_C_OFST 3 +#define POWER_VCC_D 0x10UL +#define POWER_VCC_D_MSK 0x10UL +#define POWER_VCC_D_OFST 4 + +/* REG Status_Reg */ +#define STATUS_REG 0x8004UL +#define PATTERN_RUNNING 0x1UL +#define PATTERN_RUNNING_MSK 0x1UL +#define PATTERN_RUNNING_OFST 0 +#define RX_BUSY 0x2UL +#define RX_BUSY_MSK 0x2UL +#define RX_BUSY_OFST 1 +#define PROCESSING_BUSY 0x4UL +#define PROCESSING_BUSY_MSK 0x4UL +#define PROCESSING_BUSY_OFST 2 +#define UDP_GEN_BUSY 0x8UL +#define UDP_GEN_BUSY_MSK 0x8UL +#define UDP_GEN_BUSY_OFST 3 +#define NETWORK_BUSY 0x10UL +#define NETWORK_BUSY_MSK 0x10UL +#define NETWORK_BUSY_OFST 4 +#define WAIT_FOR_TRIGGER 0x20UL +#define WAIT_FOR_TRIGGER_MSK 0x20UL +#define WAIT_FOR_TRIGGER_OFST 5 +#define RX_NOT_GOOD 0x40UL +#define RX_NOT_GOOD_MSK 0x40UL +#define RX_NOT_GOOD_OFST 6 + +/* REG Status_Reg2 */ +#define STATUS_REG2 0x8008UL +#define STATUS_REG2_PRESET 0x0UL + +/* REG FPGAVersionReg */ +#define FPGAVERSIONREG 0x800cUL +#define FPGACOMPDATE_MSK 0xffffffUL +#define FPGACOMPDATE_OFST 0 +#define FPGADETTYPE_MSK 0xff000000UL +#define FPGADETTYPE_OFST 24 +#define FPGADETTYPE_PRESET 0x8UL + +/* REG FPGA_GIT_HEAD */ +#define FPGA_GIT_HEAD 0x8010UL +#define FPGA_GIT_HEAD_PRESET 0x0UL + +/* REG FixedPatternReg */ +#define FIXEDPATTERNREG 0x8014UL +#define FIXEDPATTERNREG_PRESET 0xacdc2016UL + +/* REG ApiVersionReg */ +#define APIVERSIONREG 0x8018UL +#define APICOMPDATE_MSK 0xffffffUL +#define APICOMPDATE_OFST 0 +#define APIDETTYPE_MSK 0xff000000UL +#define APIDETTYPE_OFST 24 +#define APIDETTYPE_PRESET 0x8UL + +/* REG datagen_ctrl */ +#define DATAGEN_CTRL 0xc300UL +#define DATAGEN_MH1_ENABLE 0x1UL +#define DATAGEN_MH1_ENABLE_MSK 0x1UL +#define DATAGEN_MH1_ENABLE_OFST 0 +#define DATAGEN_MH1_RESETN 0x2UL +#define DATAGEN_MH1_RESETN_MSK 0x2UL +#define DATAGEN_MH1_RESETN_OFST 1 + +/* REG FIFO_To_Gb_Control_Reg */ +#define FIFO_TO_GB_CONTROL_REG 0xa000UL +#define ENABLED_CHANNELS_ADC_MSK 0xffUL +#define ENABLED_CHANNELS_ADC_OFST 0 +#define ENABLED_CHANNELS_D 0x100UL +#define ENABLED_CHANNELS_D_MSK 0x100UL +#define ENABLED_CHANNELS_D_OFST 8 +#define ENABLED_CHANNELS_X_MSK 0x1e00UL +#define ENABLED_CHANNELS_X_OFST 9 +#define RO_MODE_ADC 0x2000UL +#define RO_MODE_ADC_MSK 0x2000UL +#define RO_MODE_ADC_OFST 13 +#define RO_MODE_D 0x4000UL +#define RO_MODE_D_MSK 0x4000UL +#define RO_MODE_D_OFST 14 +#define RO_MODE_X 0x8000UL +#define RO_MODE_X_MSK 0x8000UL +#define RO_MODE_X_OFST 15 +#define COUNT_FRAMES_FROM_UPDATE 0x10000UL +#define COUNT_FRAMES_FROM_UPDATE_MSK 0x10000UL +#define COUNT_FRAMES_FROM_UPDATE_OFST 16 +#define START_STREAMING_P 0x20000UL +#define START_STREAMING_P_MSK 0x20000UL +#define START_STREAMING_P_OFST 17 +#define STREAM_BUFFER_CLEAR 0x40000UL +#define STREAM_BUFFER_CLEAR_MSK 0x40000UL +#define STREAM_BUFFER_CLEAR_OFST 18 + +/* REG no_Samples_D_Reg */ +#define NO_SAMPLES_D_REG 0xa004UL +#define NO_SAMPLES_D_MSK 0x3fffUL +#define NO_SAMPLES_D_OFST 0 + +/* REG no_Samples_A_Reg */ +#define NO_SAMPLES_A_REG 0xa008UL +#define NO_SAMPLES_A_MSK 0x3fffUL +#define NO_SAMPLES_A_OFST 0 + +/* REG no_Samples_X_Reg */ +#define NO_SAMPLES_X_REG 0xa00cUL +#define NO_SAMPLES_X_MSK 0x1fffUL +#define NO_SAMPLES_X_OFST 0 + +/* REG count_Frames_From_Reg_1 */ +#define COUNT_FRAMES_FROM_REG_1 0xa010UL +#define COUNT_FRAMES_FROM_REG_1_PRESET 0x0UL + +/* REG count_Frames_From_Reg_2 */ +#define COUNT_FRAMES_FROM_REG_2 0xa014UL +#define COUNT_FRAMES_FROM_REG_2_PRESET 0x0UL + +/* REG local_Frame_Number_Reg_1 */ +#define LOCAL_FRAME_NUMBER_REG_1 0xa018UL +#define LOCAL_FRAME_NUMBER_REG_1_PRESET 0x0UL + +/* REG local_Frame_Number_Reg_2 */ +#define LOCAL_FRAME_NUMBER_REG_2 0xa01cUL +#define LOCAL_FRAME_NUMBER_REG_2_PRESET 0x0UL + +/* REG TransceiverRXCTRL0Reg1 */ +#define TRANSCEIVERRXCTRL0REG1 0xc100UL +#define TRANSCEIVERRXCTRL0REG1_PRESET 0x0UL + +/* REG TransceiverRXCTRL0Reg2 */ +#define TRANSCEIVERRXCTRL0REG2 0xc104UL +#define TRANSCEIVERRXCTRL0REG2_PRESET 0x0UL + +/* REG TransceiverRXCTRL1Reg1 */ +#define TRANSCEIVERRXCTRL1REG1 0xc108UL +#define TRANSCEIVERRXCTRL1REG1_PRESET 0x0UL + +/* REG TransceiverRXCTRL1Reg2 */ +#define TRANSCEIVERRXCTRL1REG2 0xc10cUL +#define TRANSCEIVERRXCTRL1REG2_PRESET 0x0UL + +/* REG TransceiverRXCTRL2Reg */ +#define TRANSCEIVERRXCTRL2REG 0xc110UL +#define TRANSCEIVERRXCTRL2REG_PRESET 0x0UL + +/* REG TransceiverRXCTRL3Reg */ +#define TRANSCEIVERRXCTRL3REG 0xc114UL +#define TRANSCEIVERRXCTRL3REG_PRESET 0x0UL + +/* REG TransceiverSTATUS */ +#define TRANSCEIVERSTATUS 0xc118UL +#define LINKDOWNLATCHEDOUT 0x1UL +#define LINKDOWNLATCHEDOUT_MSK 0x1UL +#define LINKDOWNLATCHEDOUT_OFST 0 +#define TXUSERCLKACTIVE 0x2UL +#define TXUSERCLKACTIVE_MSK 0x2UL +#define TXUSERCLKACTIVE_OFST 1 +#define RXUSERCLKACTIVE 0x4UL +#define RXUSERCLKACTIVE_MSK 0x4UL +#define RXUSERCLKACTIVE_OFST 2 +#define RXCOMMADET_MSK 0x78UL +#define RXCOMMADET_OFST 3 +#define RXBYTEREALIGN_MSK 0x780UL +#define RXBYTEREALIGN_OFST 7 +#define RXBYTEISALIGNED_MSK 0x7800UL +#define RXBYTEISALIGNED_OFST 11 +#define GTWIZRXCDRSTABLE 0x8000UL +#define GTWIZRXCDRSTABLE_MSK 0x8000UL +#define GTWIZRXCDRSTABLE_OFST 15 +#define RESETTXDONE 0x10000UL +#define RESETTXDONE_MSK 0x10000UL +#define RESETTXDONE_OFST 16 +#define RESETRXDONE 0x20000UL +#define RESETRXDONE_MSK 0x20000UL +#define RESETRXDONE_OFST 17 +#define RXPMARESETDONE_MSK 0x3c0000UL +#define RXPMARESETDONE_OFST 18 +#define TXPMARESETDONE_MSK 0x3c00000UL +#define TXPMARESETDONE_OFST 22 +#define GTTPOWERGOOD_MSK 0x3c000000UL +#define GTTPOWERGOOD_OFST 26 + +/* REG TransceiverSTATUS2 */ +#define TRANSCEIVERSTATUS2 0xc11cUL +#define RXLOCKED_MSK 0xfUL +#define RXLOCKED_OFST 0 + +/* REG TransceiverCONTROL */ +#define TRANSCEIVERCONTROL 0xc120UL +#define GTWIZRESETALL 0x1UL +#define GTWIZRESETALL_MSK 0x1UL +#define GTWIZRESETALL_OFST 0 +#define RESETTXPLLANDDATAPATH 0x2UL +#define RESETTXPLLANDDATAPATH_MSK 0x2UL +#define RESETTXPLLANDDATAPATH_OFST 1 +#define RESETTXDATAPATHIN 0x4UL +#define RESETTXDATAPATHIN_MSK 0x4UL +#define RESETTXDATAPATHIN_OFST 2 +#define RESETRXPLLANDDATAPATH 0x8UL +#define RESETRXPLLANDDATAPATH_MSK 0x8UL +#define RESETRXPLLANDDATAPATH_OFST 3 +#define RESETRXDATAPATHIN 0x10UL +#define RESETRXDATAPATHIN_MSK 0x10UL +#define RESETRXDATAPATHIN_OFST 4 +#define RXPOLARITY_MSK 0x1e0UL +#define RXPOLARITY_OFST 5 +#define RXERRORCNTRESET_MSK 0x1e00UL +#define RXERRORCNTRESET_OFST 9 +#define RXMSBLSBINVERT_MSK 0x1e000UL +#define RXMSBLSBINVERT_OFST 13 +#define RXWORDALIGNINVERT_MSK 0x1e0000UL +#define RXWORDALIGNINVERT_OFST 17 +#define ENABLEDVALIDLOCK 0x200000UL +#define ENABLEDVALIDLOCK_MSK 0x200000UL +#define ENABLEDVALIDLOCK_OFST 21 +#define ENABLEMANUALWORDALIGN 0x400000UL +#define ENABLEMANUALWORDALIGN_MSK 0x400000UL +#define ENABLEMANUALWORDALIGN_OFST 22 + +/* REG TransceiverErrCnt_Reg0 */ +#define TRANSCEIVERERRCNT_REG0 0xc124UL +#define TRANSCEIVERERRCNT_REG0_PRESET 0x0UL + +/* REG TransceiverErrCnt_Reg1 */ +#define TRANSCEIVERERRCNT_REG1 0xc128UL +#define TRANSCEIVERERRCNT_REG1_PRESET 0x0UL + +/* REG TransceiverErrCnt_Reg2 */ +#define TRANSCEIVERERRCNT_REG2 0xc12cUL +#define TRANSCEIVERERRCNT_REG2_PRESET 0x0UL + +/* REG TransceiverErrCnt_Reg3 */ +#define TRANSCEIVERERRCNT_REG3 0xc130UL +#define TRANSCEIVERERRCNT_REG3_PRESET 0x0UL + +/* REG TransceiverAlignCnt_Reg0 */ +#define TRANSCEIVERALIGNCNT_REG0 0xc134UL +#define RXALIGNCNTCH0_MSK 0xffffUL +#define RXALIGNCNTCH0_OFST 0 + +/* REG TransceiverAlignCnt_Reg1 */ +#define TRANSCEIVERALIGNCNT_REG1 0xc138UL +#define RXALIGNCNTCH1_MSK 0xffffUL +#define RXALIGNCNTCH1_OFST 0 + +/* REG TransceiverAlignCnt_Reg2 */ +#define TRANSCEIVERALIGNCNT_REG2 0xc13cUL +#define RXALIGNCNTCH2_MSK 0xffffUL +#define RXALIGNCNTCH2_OFST 0 + +/* REG TransceiverAlignCnt_Reg3 */ +#define TRANSCEIVERALIGNCNT_REG3 0xc140UL +#define RXALIGNCNTCH3_MSK 0xffffUL +#define RXALIGNCNTCH3_OFST 0 + +/* REG TransceiverLastWord_Reg0 */ +#define TRANSCEIVERLASTWORD_REG0 0xc144UL +#define RXDATACH0_MSK 0xffffUL +#define RXDATACH0_OFST 0 + +/* REG TransceiverLastWord_Reg1 */ +#define TRANSCEIVERLASTWORD_REG1 0xc148UL +#define RXDATACH1_MSK 0xffffUL +#define RXDATACH1_OFST 0 + +/* REG TransceiverLastWord_Reg2 */ +#define TRANSCEIVERLASTWORD_REG2 0xc14cUL +#define RXDATACH2_MSK 0xffffUL +#define RXDATACH2_OFST 0 + +/* REG TransceiverLastWord_Reg3 */ +#define TRANSCEIVERLASTWORD_REG3 0xc150UL +#define RXDATACH3_MSK 0xffffUL +#define RXDATACH3_OFST 0 + +/* REG PktPacketLengthReg */ +#define PKTPACKETLENGTHREG 0xa020UL +#define PACKETLENGTH1G_MSK 0xffffUL +#define PACKETLENGTH1G_OFST 0 +#define PACKETLENGTH10G_MSK 0xffff0000UL +#define PACKETLENGTH10G_OFST 16 + +/* REG PktNoPacketsReg */ +#define PKTNOPACKETSREG 0xa024UL +#define NOPACKETS1G_MSK 0x3fUL +#define NOPACKETS1G_OFST 0 +#define NOPACKETS10G_MSK 0x3f0000UL +#define NOPACKETS10G_OFST 16 + +/* REG PktCtrlReg */ +#define PKTCTRLREG 0xa028UL +#define NOSERVERS_MSK 0x3fUL +#define NOSERVERS_OFST 0 +#define SERVERSTART_MSK 0x1f00UL +#define SERVERSTART_OFST 8 +#define ETHINTERF 0x10000UL +#define ETHINTERF_MSK 0x10000UL +#define ETHINTERF_OFST 16 + +/* REG PktCoordReg1 */ +#define PKTCOORDREG1 0xa02cUL +#define COORDX_MSK 0xffffUL +#define COORDX_OFST 0 +#define COORDY_MSK 0xffff0000UL +#define COORDY_OFST 16 + +/* REG PktCoordReg2 */ +#define PKTCOORDREG2 0xa030UL +#define COORDZ_MSK 0xffffUL +#define COORDZ_OFST 0 + +/* REG pattern_out_lsb_reg */ +#define PATTERN_OUT_LSB_REG 0xb000UL +#define PATTERN_OUT_LSB_REG_PRESET 0x0UL + +/* REG pattern_out_msb_reg */ +#define PATTERN_OUT_MSB_REG 0xb004UL +#define PATTERN_OUT_MSB_REG_PRESET 0x0UL + +/* REG pattern_in_lsb_reg */ +#define PATTERN_IN_LSB_REG 0xb008UL +#define PATTERN_IN_LSB_REG_PRESET 0x0UL + +/* REG pattern_in_msb_reg */ +#define PATTERN_IN_MSB_REG 0xb00cUL +#define PATTERN_IN_MSB_REG_PRESET 0x0UL + +/* REG pattern_mask_lsb_reg */ +#define PATTERN_MASK_LSB_REG 0xb010UL +#define PATTERN_MASK_LSB_REG_PRESET 0x0UL + +/* REG pattern_mask_msb_reg */ +#define PATTERN_MASK_MSB_REG 0xb014UL +#define PATTERN_MASK_MSB_REG_PRESET 0x0UL + +/* REG pattern_set_lsb_reg */ +#define PATTERN_SET_LSB_REG 0xb018UL +#define PATTERN_SET_LSB_REG_PRESET 0x0UL + +/* REG pattern_set_msb_reg */ +#define PATTERN_SET_MSB_REG 0xb01cUL +#define PATTERN_SET_MSB_REG_PRESET 0x0UL + +/* REG pattern_cntrl_reg */ +#define PATTERN_CNTRL_REG 0xb020UL +#define PATTERN_CNTRL_WR 0x1UL +#define PATTERN_CNTRL_WR_MSK 0x1UL +#define PATTERN_CNTRL_WR_OFST 0 +#define PATTERN_CNTRL_RD 0x2UL +#define PATTERN_CNTRL_RD_MSK 0x2UL +#define PATTERN_CNTRL_RD_OFST 1 +#define PATTERN_CNTRL_ADDR_MSK 0x1fff0000UL +#define PATTERN_CNTRL_ADDR_OFST 16 + +/* REG pattern_limit_reg */ +#define PATTERN_LIMIT_REG 0xb024UL +#define PATTERN_LIMIT_STRT_MSK 0x1fffUL +#define PATTERN_LIMIT_STRT_OFST 0 +#define PATTERN_LIMIT_STP_MSK 0x1fff0000UL +#define PATTERN_LIMIT_STP_OFST 16 + +/* REG pattern_io_cntrl_lsb_reg */ +#define PATTERN_IO_CNTRL_LSB_REG 0xb028UL +#define PATTERN_IO_CNTRL_LSB_REG_PRESET 0x0UL + +/* REG pattern_io_cntrl_msb_reg */ +#define PATTERN_IO_CNTRL_MSB_REG 0xb02cUL +#define PATTERN_IO_CNTRL_MSB_REG_PRESET 0x0UL + +/* REG Flow_Control_Reg */ +#define FLOW_CONTROL_REG 0xb030UL +#define START_F 0x1UL +#define START_F_MSK 0x1UL +#define START_F_OFST 0 +#define STOP_F 0x2UL +#define STOP_F_MSK 0x2UL +#define STOP_F_OFST 1 +#define RST_F 0x4UL +#define RST_F_MSK 0x4UL +#define RST_F_OFST 2 +#define SW_TRIGGER_F 0x8UL +#define SW_TRIGGER_F_MSK 0x8UL +#define SW_TRIGGER_F_OFST 3 +#define TRIGGER_ENABLE 0x10UL +#define TRIGGER_ENABLE_MSK 0x10UL +#define TRIGGER_ENABLE_OFST 4 +#define RSM_BUSY 0x20UL +#define RSM_BUSY_MSK 0x20UL +#define RSM_BUSY_OFST 5 +#define RSM_TRG_WAIT 0x40UL +#define RSM_TRG_WAIT_MSK 0x40UL +#define RSM_TRG_WAIT_OFST 6 +#define CSM_BUSY 0x80UL +#define CSM_BUSY_MSK 0x80UL +#define CSM_BUSY_OFST 7 + +/* REG delay_In_Reg_1 */ +#define DELAY_IN_REG_1 0xb034UL +#define DELAY_IN_REG_1_PRESET 0x0UL + +/* REG delay_In_Reg_2 */ +#define DELAY_IN_REG_2 0xb038UL +#define DELAY_IN_REG_2_PRESET 0x0UL + +/* REG cycles_In_Reg_1 */ +#define CYCLES_IN_REG_1 0xb03cUL +#define CYCLES_IN_REG_1_PRESET 0x0UL + +/* REG cycles_In_Reg_2 */ +#define CYCLES_IN_REG_2 0xb040UL +#define CYCLES_IN_REG_2_PRESET 0x0UL + +/* REG frames_In_Reg_1 */ +#define FRAMES_IN_REG_1 0xb044UL +#define FRAMES_IN_REG_1_PRESET 0x0UL + +/* REG frames_In_Reg_2 */ +#define FRAMES_IN_REG_2 0xb048UL +#define FRAMES_IN_REG_2_PRESET 0x0UL + +/* REG period_In_Reg_1 */ +#define PERIOD_IN_REG_1 0xb04cUL +#define PERIOD_IN_REG_1_PRESET 0x0UL + +/* REG period_In_Reg_2 */ +#define PERIOD_IN_REG_2 0xb050UL +#define PERIOD_IN_REG_2_PRESET 0x0UL + +/* REG pattern_test_reg */ +#define PATTERN_TEST_REG 0xb054UL +#define PATTERN_TEST_REG_PRESET 0x0UL + +/* REG pattern_firmware_reg */ +#define PATTERN_FIRMWARE_REG 0xb058UL +#define PATTERN_WIDTH_MSK 0xffUL +#define PATTERN_WIDTH_OFST 0 +#define PATTERN_ADDR_WIDTH_MSK 0xff00UL +#define PATTERN_ADDR_WIDTH_OFST 8 +#define PATTERN_NLOOPS_NWAITS_MSK 0xff0000UL +#define PATTERN_NLOOPS_NWAITS_OFST 16 +#define DIRECT_PATTERN_RAM 0x1000000UL +#define DIRECT_PATTERN_RAM_MSK 0x1000000UL +#define DIRECT_PATTERN_RAM_OFST 24 + +/* REG time_From_Start_Out_Reg_1 */ +#define TIME_FROM_START_OUT_REG_1 0xb05cUL +#define TIME_FROM_START_OUT_REG_1_PRESET 0x0UL + +/* REG time_From_Start_Out_Reg_2 */ +#define TIME_FROM_START_OUT_REG_2 0xb060UL +#define TIME_FROM_START_OUT_REG_2_PRESET 0x0UL + +/* REG frames_From_Start_Out_Reg_1 */ +#define FRAMES_FROM_START_OUT_REG_1 0xb064UL +#define FRAMES_FROM_START_OUT_REG_1_PRESET 0x0UL + +/* REG frames_From_Start_Out_Reg_2 */ +#define FRAMES_FROM_START_OUT_REG_2 0xb068UL +#define FRAMES_FROM_START_OUT_REG_2_PRESET 0x0UL + +/* REG frame_Time_Out_Reg_1 */ +#define FRAME_TIME_OUT_REG_1 0xb06cUL +#define FRAME_TIME_OUT_REG_1_PRESET 0x0UL + +/* REG frame_Time_Out_Reg_2 */ +#define FRAME_TIME_OUT_REG_2 0xb070UL +#define FRAME_TIME_OUT_REG_2_PRESET 0x0UL + +/* REG pattern_loopdef_base */ +#define PATTERN_LOOPDEF_BASE 0xb080UL +#define PATTERN_LOOP_ADDR_WORD 0x1UL +#define PATTERN_LOOP_ADDR_WORD_MSK 0x1UL +#define PATTERN_LOOP_ADDR_WORD_OFST 0 +#define PATTERN_LOOP_ITERATION_WORD 0x2UL +#define PATTERN_LOOP_ITERATION_WORD_MSK 0x2UL +#define PATTERN_LOOP_ITERATION_WORD_OFST 1 +#define PATTERN_WAIT_ADDR_WORD 0x4UL +#define PATTERN_WAIT_ADDR_WORD_MSK 0x4UL +#define PATTERN_WAIT_ADDR_WORD_OFST 2 +#define PATTERN_WAIT_TIMER_LSB_WORD 0x8UL +#define PATTERN_WAIT_TIMER_LSB_WORD_MSK 0x8UL +#define PATTERN_WAIT_TIMER_LSB_WORD_OFST 3 +#define PATTERN_WAIT_TIMER_MSB_WORD 0x10UL +#define PATTERN_WAIT_TIMER_MSB_WORD_MSK 0x10UL +#define PATTERN_WAIT_TIMER_MSB_WORD_OFST 4 +#define PATTERN_LOOPDEF_NWORDS 0x20UL +#define PATTERN_LOOPDEF_NWORDS_MSK 0x20UL +#define PATTERN_LOOPDEF_NWORDS_OFST 5 + +/* REG pattern_loopdef_base_helper1 */ +#define PATTERN_LOOPDEF_BASE_HELPER1 0xb084UL +#define PATTERN_WAIT_ADDR_MSK 0x1fffUL +#define PATTERN_WAIT_ADDR_OFST 0 + +/* REG pattern_loopdef_base_helper2 */ +#define PATTERN_LOOPDEF_BASE_HELPER2 0xb088UL +#define PATTERN_LOOP_ADDR_STRT_MSK 0x1fffUL +#define PATTERN_LOOP_ADDR_STRT_OFST 0 +#define PATTERN_LOOP_ADDR_STP_MSK 0x1fff0000UL +#define PATTERN_LOOP_ADDR_STP_OFST 16 + +/* REG pattern_bypass */ +#define PATTERN_BYPASS 0xc200UL +#define PATTERN_BYPASS_PRESET 0x0UL + +/* REG pattern_bypass_enable */ +#define PATTERN_BYPASS_ENABLE 0xc204UL +#define PATTERN_BYPASS_ENABLE_PRESET 0x0UL + +/* REG pattern_MOSI_bitselect */ +#define PATTERN_MOSI_BITSELECT 0xc208UL +#define PATTERN_MOSI_BITSELECT_PRESET 0x0UL + +/* REG pattern_SCLK_bitselect */ +#define PATTERN_SCLK_BITSELECT 0xc20cUL +#define PATTERN_SCLK_BITSELECT_PRESET 0x0UL + +/* REG pattern_SPI_writedata */ +#define PATTERN_SPI_WRITEDATA 0xc210UL +#define PATTERN_SPI_WRITEDATA_PRESET 0x0UL + +/* REG pattern_mux_ctrl */ +#define PATTERN_MUX_CTRL 0xc214UL +#define SPI_FULL 0x2UL +#define SPI_FULL_MSK 0x2UL +#define SPI_FULL_OFST 1 +#define MISO_FIFO_CLEAR 0x4UL +#define MISO_FIFO_CLEAR_MSK 0x4UL +#define MISO_FIFO_CLEAR_OFST 2 +#define MISO_FIFO_FULL 0x8UL +#define MISO_FIFO_FULL_MSK 0x8UL +#define MISO_FIFO_FULL_OFST 3 +#define MISO_FIFO_EMPTY 0x10UL +#define MISO_FIFO_EMPTY_MSK 0x10UL +#define MISO_FIFO_EMPTY_OFST 4 +#define ENABLE_CPU_SPI 0x20UL +#define ENABLE_CPU_SPI_MSK 0x20UL +#define ENABLE_CPU_SPI_OFST 5 +#define SPI_REVERSE_BITORDER 0x40UL +#define SPI_REVERSE_BITORDER_MSK 0x40UL +#define SPI_REVERSE_BITORDER_OFST 6 + +/* REG MISO_data */ +#define MISO_DATA 0xc218UL +#define MISO_DATA_PRESET 0x0UL + +/* REG pattern_CSN_bitselect */ +#define PATTERN_CSN_BITSELECT 0xc21cUL +#define PATTERN_CSN_BITSELECT_PRESET 0x0UL + +/* REG SPI_nBits */ +#define SPI_NBITS 0xc220UL +#define SPI_NBITS_MSK 0x1fUL +#define SPI_NBITS_OFST 0 + +/* REG DbitFIFOCTRLReg */ +#define DBITFIFOCTRLREG 0xc000UL +#define DBITRD 0x1UL +#define DBITRD_MSK 0x1UL +#define DBITRD_OFST 0 +#define DBITRST 0x2UL +#define DBITRST_MSK 0x2UL +#define DBITRST_OFST 1 +#define DBITFULL 0x4UL +#define DBITFULL_MSK 0x4UL +#define DBITFULL_OFST 2 +#define DBITEMPTY 0x8UL +#define DBITEMPTY_MSK 0x8UL +#define DBITEMPTY_OFST 3 +#define DBITUNDERFLOW 0x10UL +#define DBITUNDERFLOW_MSK 0x10UL +#define DBITUNDERFLOW_OFST 4 +#define DBITOVERFLOW 0x20UL +#define DBITOVERFLOW_MSK 0x20UL +#define DBITOVERFLOW_OFST 5 + +/* REG DbitFIFODataReg1 */ +#define DBITFIFODATAREG1 0xc004UL +#define DBITFIFODATAREG1_PRESET 0x0UL + +/* REG DbitFIFODataReg2 */ +#define DBITFIFODATAREG2 0xc008UL +#define DBITFIFODATAREG2_PRESET 0x0UL + +/* REG MatterhornSPIReg1 */ +#define MATTERHORNSPIREG1 0xc00cUL +#define MATTERHORNSPIREG1_PRESET 0x0UL + +/* REG MatterhornSPIReg2 */ +#define MATTERHORNSPIREG2 0xc010UL +#define MATTERHORNSPIREG2_PRESET 0x0UL + +/* REG MatterhornSPICTRL */ +#define MATTERHORNSPICTRL 0xc014UL +#define CONFIGSTART_P 0x1UL +#define CONFIGSTART_P_MSK 0x1UL +#define CONFIGSTART_P_OFST 0 +#define PERIPHERYRST_P 0x2UL +#define PERIPHERYRST_P_MSK 0x2UL +#define PERIPHERYRST_P_OFST 1 +#define STARTREAD_P 0x4UL +#define STARTREAD_P_MSK 0x4UL +#define STARTREAD_P_OFST 2 +#define BUSY 0x8UL +#define BUSY_MSK 0x8UL +#define BUSY_OFST 3 +#define READOUTFROMASIC 0x10UL +#define READOUTFROMASIC_MSK 0x10UL +#define READOUTFROMASIC_OFST 4 + +/* REG MISO_select */ +#define MISO_SELECT 0xc018UL +#define MISO_SELECT_PRESET 0x0UL + +/* REG A_FIFO_Overflow_Status_Reg */ +#define A_FIFO_OVERFLOW_STATUS_REG 0x9000UL +#define A_FIFO_OVERFLOW_STATUS_REG_PRESET 0x0UL + +/* REG A_FIFO_Empty_Status_Reg */ +#define A_FIFO_EMPTY_STATUS_REG 0x9004UL +#define A_FIFO_EMPTY_STATUS_REG_PRESET 0x0UL + +/* REG A_FIFO_Full_Status_Reg */ +#define A_FIFO_FULL_STATUS_REG 0x9008UL +#define A_FIFO_FULL_STATUS_REG_PRESET 0x0UL + +/* REG D_FIFO_Overflow_Status_Reg */ +#define D_FIFO_OVERFLOW_STATUS_REG 0x900cUL +#define D_FIFO_OVERFLOW_STATUS 0x1UL +#define D_FIFO_OVERFLOW_STATUS_MSK 0x1UL +#define D_FIFO_OVERFLOW_STATUS_OFST 0 + +/* REG D_FIFO_Empty_Status_Reg */ +#define D_FIFO_EMPTY_STATUS_REG 0x9010UL +#define D_FIFO_EMPTY_STATUS 0x1UL +#define D_FIFO_EMPTY_STATUS_MSK 0x1UL +#define D_FIFO_EMPTY_STATUS_OFST 0 + +/* REG D_FIFO_Full_Status_Reg */ +#define D_FIFO_FULL_STATUS_REG 0x9014UL +#define D_FIFO_FULL_STATUS 0x1UL +#define D_FIFO_FULL_STATUS_MSK 0x1UL +#define D_FIFO_FULL_STATUS_OFST 0 + +/* REG X_FIFO_Overflow_Status_Reg */ +#define X_FIFO_OVERFLOW_STATUS_REG 0x9018UL +#define X_FIFO_OVERFLOW_STATUS_MSK 0xfUL +#define X_FIFO_OVERFLOW_STATUS_OFST 0 + +/* REG X_FIFO_Empty_Status_Reg */ +#define X_FIFO_EMPTY_STATUS_REG 0x901cUL +#define X_FIFO_EMPTY_STATUS_MSK 0xfUL +#define X_FIFO_EMPTY_STATUS_OFST 0 + +/* REG X_FIFO_Full_Status_Reg */ +#define X_FIFO_FULL_STATUS_REG 0x9020UL +#define X_FIFO_FULL_STATUS_MSK 0xfUL +#define X_FIFO_FULL_STATUS_OFST 0 + +/* REG A_FIFO_Clean_Reg */ +#define A_FIFO_CLEAN_REG 0x9024UL +#define A_FIFO_CLEAN_REG_PRESET 0x0UL + +/* REG D_FIFO_Clean_Reg */ +#define D_FIFO_CLEAN_REG 0x9028UL +#define D_FIFO_CLEAN 0x1UL +#define D_FIFO_CLEAN_MSK 0x1UL +#define D_FIFO_CLEAN_OFST 0 + +/* REG X_FIFO_Clean_Reg */ +#define X_FIFO_CLEAN_REG 0x902cUL +#define X_FIFO_CLEAN_MSK 0xfUL +#define X_FIFO_CLEAN_OFST 0 + +#endif /* __CHEBY__XCTB__H__ */ // ---------------------------------------------------- // TODO: fix these in the firmware reg generator: // ----------------------------------------------------: diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer b/slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer index d28cb6db7..2b82c81db 100755 Binary files a/slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer and b/slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer differ diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c index 992d11f18..c8b338a87 100644 --- a/slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c @@ -9,8 +9,8 @@ #include "sls/versionAPI.h" #include "LTC2620_Driver.h" +#include "XILINX_FMC.h" #include "XILINX_PLL.h" - #include "loadPattern.h" #ifdef VIRTUAL #include "communication_funcs_UDP.h" @@ -257,17 +257,17 @@ int testFixedFPGAPattern() { LOG(logINFO, ("Testing FPGA Fixed Pattern:\n")); #ifndef VIRTUAL uint32_t val = bus_r(FIXEDPATTERNREG); - if (val == FIXEDPATTERNVAL) { + if (val == FIXEDPATTERNREG_PRESET) { LOG(logINFO, ("\tFixed pattern: successful match (0x%08x)\n", val)); } else { LOG(logERROR, ("Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n", - val, FIXEDPATTERNVAL)); + val, FIXEDPATTERNREG_PRESET)); return FAIL; } #endif - LOG(logINFO, - ("\tSuccessfully read FPGA Fixed Pattern (0x%x)\n", FIXEDPATTERNVAL)); + LOG(logINFO, ("\tSuccessfully read FPGA Fixed Pattern (0x%x)\n", + FIXEDPATTERNREG_PRESET)); return OK; } @@ -405,6 +405,13 @@ void setupDetector() { LTC2620_D_SetDefines(DAC_MIN_MV, DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC, NPWR, DAC_POWERDOWN_DRIVER_FILE_NAME); + + // power LTC2620 before talking to it: + initError = XILINX_FMC_enable_all(initErrorMessage, MAX_STR_LENGTH); + if (initError == FAIL) { + return; + } + LOG(logINFOBLUE, ("Powering down all dacs\n")); for (int idac = 0; idac < NDAC; ++idac) { setDAC(idac, LTC2620_D_GetPowerDownValue(), 0); @@ -579,9 +586,10 @@ int powerChip(int on, char *mess) { } else { LOG(logINFOBLUE, ("Powering chip: off\n")); bus_w(addr, bus_r(addr) & ~mask); - chipConfigured = 0; - + if (FAIL == XILINX_FMC_disable_all(mess, MAX_STR_LENGTH)) { + return FAIL; + } #ifdef VIRTUAL setTransceiverAlignment(0); #endif diff --git a/slsSupportLib/include/sls/sls_detector_defs.h b/slsSupportLib/include/sls/sls_detector_defs.h index 192cbf3ce..a5ccb2566 100644 --- a/slsSupportLib/include/sls/sls_detector_defs.h +++ b/slsSupportLib/include/sls/sls_detector_defs.h @@ -804,7 +804,7 @@ typedef struct { } sls_detector_module &operator=(const sls_detector_module &other) { - if(this == &other) + if (this == &other) return *this; delete[] dacs; delete[] chanregs; diff --git a/slsSupportLib/include/sls/versionAPI.h b/slsSupportLib/include/sls/versionAPI.h index 075fd280b..2911477d9 100644 --- a/slsSupportLib/include/sls/versionAPI.h +++ b/slsSupportLib/include/sls/versionAPI.h @@ -7,6 +7,6 @@ #define APIGOTTHARD2 "0.0.0 0x250909" #define APIMOENCH "0.0.0 0x250909" #define APIEIGER "0.0.0 0x250909" -#define APIXILINXCTB "0.0.0 0x251015" +#define APIXILINXCTB "0.0.0 0x260106" #define APIJUNGFRAU "0.0.0 0x250909" #define APIMYTHEN3 "0.0.0 0x250922"