diff --git a/slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer b/slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer index 1ffc0f30a..c36b21684 100755 Binary files a/slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer and b/slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer differ diff --git a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c index 69a7e563c..a0bbfa4b7 100755 --- a/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c @@ -52,7 +52,7 @@ char volatile *digitalDataPtr = 0; char udpPacketData[UDP_PACKET_DATA_BYTES + sizeof(sls_detector_header)]; int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0}; -uint32_t clkDivider[NUM_CLOCKS] = {40, 20, 20, 200}; +uint32_t clkFrequency[NUM_CLOCKS] = {40, 20, 20, 200}; int dacValues[NDAC] = {0}; // software limit that depends on the current chip on the ctb @@ -457,10 +457,10 @@ void setupDetector() { for (i = 0; i < NUM_CLOCKS; ++i) { clkPhase[i] = 0; } - clkDivider[RUN_CLK] = DEFAULT_RUN_CLK; - clkDivider[ADC_CLK] = DEFAULT_ADC_CLK; - clkDivider[SYNC_CLK] = DEFAULT_SYNC_CLK; - clkDivider[DBIT_CLK] = DEFAULT_DBIT_CLK; + clkFrequency[RUN_CLK] = DEFAULT_RUN_CLK; + clkFrequency[ADC_CLK] = DEFAULT_ADC_CLK; + clkFrequency[SYNC_CLK] = DEFAULT_SYNC_CLK; + clkFrequency[DBIT_CLK] = DEFAULT_DBIT_CLK; for (i = 0; i < NDAC; ++i) dacValues[i] = -1; } @@ -842,12 +842,12 @@ int setExpTime(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val)); - val *= (1E-3 * clkDivider[RUN_CLK]); + val *= (1E-3 * clkFrequency[RUN_CLK]); setPatternWaitTime(0, val); // validate for tolerance int64_t retval = getExpTime(); - val /= (1E-3 * clkDivider[RUN_CLK]); + val /= (1E-3 * clkFrequency[RUN_CLK]); if (val != retval) { return FAIL; } @@ -855,7 +855,7 @@ int setExpTime(int64_t val) { } int64_t getExpTime() { - return setPatternWaitTime(0, -1) / (1E-3 * clkDivider[RUN_CLK]); + return setPatternWaitTime(0, -1) / (1E-3 * clkFrequency[RUN_CLK]); } int setPeriod(int64_t val) { @@ -864,12 +864,12 @@ int setPeriod(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val)); - val *= (1E-3 * clkDivider[SYNC_CLK]); + val *= (1E-3 * clkFrequency[SYNC_CLK]); set64BitReg(val, PERIOD_LSB_REG, PERIOD_MSB_REG); // validate for tolerance int64_t retval = getPeriod(); - val /= (1E-3 * clkDivider[SYNC_CLK]); + val /= (1E-3 * clkFrequency[SYNC_CLK]); if (val != retval) { return FAIL; } @@ -877,7 +877,7 @@ int setPeriod(int64_t val) { } int64_t getPeriod() { - return get64BitReg(PERIOD_LSB_REG, PERIOD_MSB_REG)/ (1E-3 * clkDivider[SYNC_CLK]); + return get64BitReg(PERIOD_LSB_REG, PERIOD_MSB_REG)/ (1E-3 * clkFrequency[SYNC_CLK]); } int setDelayAfterTrigger(int64_t val) { @@ -886,12 +886,12 @@ int setDelayAfterTrigger(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val)); - val *= (1E-3 * clkDivider[SYNC_CLK]); + val *= (1E-3 * clkFrequency[SYNC_CLK]); set64BitReg(val, DELAY_LSB_REG, DELAY_MSB_REG); // validate for tolerance int64_t retval = getDelayAfterTrigger(); - val /= (1E-3 * clkDivider[SYNC_CLK]); + val /= (1E-3 * clkFrequency[SYNC_CLK]); if (val != retval) { return FAIL; } @@ -899,7 +899,7 @@ int setDelayAfterTrigger(int64_t val) { } int64_t getDelayAfterTrigger() { - return get64BitReg(DELAY_LSB_REG, DELAY_MSB_REG) / (1E-3 * clkDivider[SYNC_CLK]); + return get64BitReg(DELAY_LSB_REG, DELAY_MSB_REG) / (1E-3 * clkFrequency[SYNC_CLK]); } int64_t getNumFramesLeft() { @@ -911,11 +911,11 @@ int64_t getNumTriggersLeft() { } int64_t getDelayAfterTriggerLeft() { - return get64BitReg(DELAY_LEFT_LSB_REG, DELAY_LEFT_MSB_REG) / (1E-3 * clkDivider[SYNC_CLK]); + return get64BitReg(DELAY_LEFT_LSB_REG, DELAY_LEFT_MSB_REG) / (1E-3 * clkFrequency[SYNC_CLK]); } int64_t getPeriodLeft() { - return get64BitReg(PERIOD_LEFT_LSB_REG, PERIOD_LEFT_MSB_REG) / (1E-3 * clkDivider[SYNC_CLK]); + return get64BitReg(PERIOD_LEFT_LSB_REG, PERIOD_LEFT_MSB_REG) / (1E-3 * clkFrequency[SYNC_CLK]); } int64_t getFramesFromStart() { @@ -1593,11 +1593,11 @@ int getMaxPhase(enum CLKINDEX ind) { FILE_LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind)); return -1; } - int ret = ((double)PLL_VCO_FREQ_MHZ / (double)clkDivider[ind]) * MAX_PHASE_SHIFTS_STEPS; + int ret = ((double)PLL_VCO_FREQ_MHZ / (double)clkFrequency[ind]) * MAX_PHASE_SHIFTS_STEPS; char* clock_names[] = {CLK_NAMES}; FILE_LOG(logDEBUG1, ("Max Phase Shift (%s): %d (Clock: %d MHz, VCO:%d MHz)\n", - clock_names[ind], ret, clkDivider[ind], PLL_VCO_FREQ_MHZ)); + clock_names[ind], ret, clkFrequency[ind], PLL_VCO_FREQ_MHZ)); return ret; } @@ -1647,8 +1647,8 @@ int setFrequency(enum CLKINDEX ind, int val) { FILE_LOG(logDEBUG1, ("\tRemembering DBIT phase: %d\n", dbitPhase)); // Calculate and set output frequency - clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val); - FILE_LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind], ind, clkDivider[ind])); + clkFrequency[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val); + FILE_LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind], ind, clkFrequency[ind])); // adc and dbit phase is reset by pll (when setting output frequency) clkPhase[ADC_CLK] = 0; @@ -1678,7 +1678,7 @@ int getFrequency(enum CLKINDEX ind) { FILE_LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind)); return -1; } - return clkDivider[ind]; + return clkFrequency[ind]; } void configureSyncFrequency(enum CLKINDEX ind) { diff --git a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer index 374ef5ee6..eb17f2c0f 100755 Binary files a/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer and b/slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer differ diff --git a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c index 33420f4c6..783aad5d3 100644 --- a/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c @@ -36,7 +36,7 @@ int virtual_stop = 0; #endif int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; -uint32_t clkDivider[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; +uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0, 0}; int highvoltage = 0; int dacValues[NDAC] = {0}; int detPos[2] = {0, 0}; @@ -329,12 +329,12 @@ void initStopServer() { void setupDetector() { FILE_LOG(logINFO, ("This Server is for 1 Gotthard2 module \n")); - clkDivider[READOUT_C0] = DEFAULT_READOUT_C0; - clkDivider[READOUT_C1] = DEFAULT_READOUT_C1; - clkDivider[SYSTEM_C0] = DEFAULT_SYSTEM_C0; - clkDivider[SYSTEM_C1] = DEFAULT_SYSTEM_C1; - clkDivider[SYSTEM_C2] = DEFAULT_SYSTEM_C2; - clkDivider[SYSTEM_C3] = DEFAULT_SYSTEM_C3; + clkFrequency[READOUT_C0] = DEFAULT_READOUT_C0; + clkFrequency[READOUT_C1] = DEFAULT_READOUT_C1; + clkFrequency[SYSTEM_C0] = DEFAULT_SYSTEM_C0; + clkFrequency[SYSTEM_C1] = DEFAULT_SYSTEM_C1; + clkFrequency[SYSTEM_C2] = DEFAULT_SYSTEM_C2; + clkFrequency[SYSTEM_C3] = DEFAULT_SYSTEM_C3; highvoltage = 0; @@ -728,11 +728,11 @@ int getMaxPhase(enum CLKINDEX ind) { } int vcofreq = getVCOFrequency(ind); int maxshiftstep = ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO(); - int ret = ((double)vcofreq / (double)clkDivider[ind]) * maxshiftstep; + int ret = ((double)vcofreq / (double)clkFrequency[ind]) * maxshiftstep; char* clock_names[] = {CLK_NAMES}; FILE_LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock: %d Hz, VCO:%d Hz)\n", - clock_names[ind], ret, clkDivider[ind], vcofreq)); + clock_names[ind], ret, clkFrequency[ind], vcofreq)); return ret; } @@ -765,7 +765,7 @@ int getFrequency(enum CLKINDEX ind) { FILE_LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind)); return -1; } - return clkDivider[ind]; + return clkFrequency[ind]; } int getVCOFrequency(enum CLKINDEX ind) { @@ -791,10 +791,10 @@ int setClockDivider(enum CLKINDEX ind, int val) { } char* clock_names[] = {CLK_NAMES}; int vcofreq = getVCOFrequency(ind); - int currentdiv = vcofreq / clkDivider[ind]; + int currentdiv = vcofreq / clkFrequency[ind]; int newfreq = vcofreq / val; - FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkDivider[ind], val, newfreq, vcofreq)); + FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq)); // Remembering old phases in degrees int oldPhases[NUM_CLOCKS]; @@ -810,8 +810,8 @@ int setClockDivider(enum CLKINDEX ind, int val) { int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL; int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind; int ret = ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq); - clkDivider[ind] = newfreq; - FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkDivider[ind])); + clkFrequency[ind] = newfreq; + FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind])); // phase is reset by pll (when setting output frequency) if (ind >= READOUT_C0) { @@ -840,7 +840,7 @@ int getClockDivider(enum CLKINDEX ind) { FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind)); return -1; } - return (getVCOFrequency(ind) / clkDivider[ind]); + return (getVCOFrequency(ind) / clkFrequency[ind]); } diff --git a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer index 773330a84..100d84674 100755 Binary files a/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer and b/slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer differ diff --git a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c index 9adefb0d2..e3d05db0a 100644 --- a/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c +++ b/slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c @@ -34,7 +34,7 @@ int virtual_stop = 0; #endif int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0}; -uint32_t clkDivider[NUM_CLOCKS] = {125, 20, 80}; +uint32_t clkFrequency[NUM_CLOCKS] = {125, 20, 80}; int highvoltage = 0; int dacValues[NDAC] = {0}; @@ -333,9 +333,9 @@ void initStopServer() { void setupDetector() { FILE_LOG(logINFO, ("This Server is for 1 Mythen3 module \n")); - clkDivider[RUN_CLK] = DEFAULT_RUN_CLK; - clkDivider[TICK_CLK] = DEFAULT_TICK_CLK; - clkDivider[SAMPLING_CLK] = DEFAULT_SAMPLING_CLK; + clkFrequency[RUN_CLK] = DEFAULT_RUN_CLK; + clkFrequency[TICK_CLK] = DEFAULT_TICK_CLK; + clkFrequency[SAMPLING_CLK] = DEFAULT_SAMPLING_CLK; highvoltage = 0; @@ -406,12 +406,12 @@ int setExpTime(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val)); - val *= (1E-3 * clkDivider[RUN_CLK]); + val *= (1E-3 * clkFrequency[RUN_CLK]); setPatternWaitTime(0, val); // validate for tolerance int64_t retval = getExpTime(); - val /= (1E-3 * clkDivider[RUN_CLK]); + val /= (1E-3 * clkFrequency[RUN_CLK]); if (val != retval) { return FAIL; } @@ -419,7 +419,7 @@ int setExpTime(int64_t val) { } int64_t getExpTime() { - return setPatternWaitTime(0, -1) / (1E-3 * clkDivider[RUN_CLK]); + return setPatternWaitTime(0, -1) / (1E-3 * clkFrequency[RUN_CLK]); } int setPeriod(int64_t val) { @@ -428,12 +428,12 @@ int setPeriod(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting period %lld ns\n", (long long int)val)); - val *= (1E-3 * clkDivider[TICK_CLK]); + val *= (1E-3 * clkFrequency[TICK_CLK]); set64BitReg(val, SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG); // validate for tolerance int64_t retval = getPeriod(); - val /= (1E-3 * clkDivider[TICK_CLK]); + val /= (1E-3 * clkFrequency[TICK_CLK]); if (val != retval) { return FAIL; } @@ -441,7 +441,7 @@ int setPeriod(int64_t val) { } int64_t getPeriod() { - return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-3 * clkDivider[TICK_CLK]); + return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-3 * clkFrequency[TICK_CLK]); } int setDelayAfterTrigger(int64_t val) { @@ -450,12 +450,12 @@ int setDelayAfterTrigger(int64_t val) { return FAIL; } FILE_LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val)); - val *= (1E-3 * clkDivider[TICK_CLK]); + val *= (1E-3 * clkFrequency[TICK_CLK]); set64BitReg(val, SET_DELAY_LSB_REG, SET_DELAY_MSB_REG); // validate for tolerance int64_t retval = getDelayAfterTrigger(); - val /= (1E-3 * clkDivider[TICK_CLK]); + val /= (1E-3 * clkFrequency[TICK_CLK]); if (val != retval) { return FAIL; } @@ -463,7 +463,7 @@ int setDelayAfterTrigger(int64_t val) { } int64_t getDelayAfterTrigger() { - return get64BitReg(SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-3 * clkDivider[TICK_CLK]); + return get64BitReg(SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-3 * clkFrequency[TICK_CLK]); } diff --git a/slsSupportLib/include/versionAPI.h b/slsSupportLib/include/versionAPI.h index a579c7006..7a76c0f6a 100644 --- a/slsSupportLib/include/versionAPI.h +++ b/slsSupportLib/include/versionAPI.h @@ -4,9 +4,9 @@ #define APIRECEIVER 0x190722 #define APIGUI 0x190723 #define APIMOENCH 0x190820 -#define APICTB 0x191106 -#define APIGOTTHARD2 0x191106 #define APIJUNGFRAU 0x191106 #define APIEIGER 0x191106 #define APIGOTTHARD 0x191106 #define APIMYTHEN3 0x191106 +#define APIGOTTHARD2 0x191106 +#define APICTB 0x191106