detector servers moved out of slsdetector software, eiger server compiles with new headers

slsDetectorServers/jungfrauDetectorServer/AD9257.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9257.h

slsDetectorServers/jungfrauDetectorServer/Makefile

@@ -0,0 +1,31 @@
+CROSS  		= bfin-uclinux-
+CC    		= $(CROSS)gcc
+CFLAGS		+=  -Wall -DJUNGFRAUD -DSLS_DETECTOR_FUNCTION_LIST  -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS		+= 	-lm  -lstdc++ 
+
+PROGS		= 	jungfrauDetectorServer 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+versioning: 
+	@echo `tput setaf 6;	./updateGitVersion.sh; tput sgr0;`
+
+$(PROGS): $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+	rm *.gdb
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o
+	
+
+	

slsDetectorServers/jungfrauDetectorServer/Makefile.virtual

@@ -0,0 +1,27 @@
+CC    		= gcc
+CFLAGS		+=  -Wall -DJUNGFRAUD -DVIRTUAL -DSLS_DETECTOR_FUNCTION_LIST  -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS		+= 	-lm  -lstdc++  -pthread
+
+PROGS		= 	jungfrauDetectorServer_virtual 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+versioning: 
+	@echo `tput setaf 6;	./updateGitVersion.sh; tput sgr0;`
+	
+$(PROGS): $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o
+	

slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h

@@ -0,0 +1,415 @@
+#ifndef REGISTER_DEFS_H
+#define REGISTER_DEFS_H
+
+/* Definitions for FPGA*/
+
+/* FPGA Version register */
+#define FPGA_VERSION_REG      			(0x00 << MEM_MAP_SHIFT)
+
+#define BOARD_REVISION_OFST				(0)
+#define BOARD_REVISION_MSK				(0x00FFFFFF << BOARD_REVISION_OFST)
+#define DETECTOR_TYPE_OFST   			(24)
+#define DETECTOR_TYPE_MSK   			(0x000000FF << DETECTOR_TYPE_OFST)
+
+
+
+/* Fix pattern register */
+#define FIX_PATT_REG          			(0x01 << MEM_MAP_SHIFT)
+
+/* Status register */
+#define STATUS_REG            			(0x02 << MEM_MAP_SHIFT)
+
+#define RUN_BUSY_OFST					(0)
+#define RUN_BUSY_MSK      				(0x00000001 << RUN_BUSY_OFST)
+#define WAITING_FOR_TRIGGER_OFST  		(3)
+#define WAITING_FOR_TRIGGER_MSK  		(0x00000001 << WAITING_FOR_TRIGGER_OFST)
+#define DELAYBEFORE_OFST  				(4)											//Not used in software
+#define DELAYBEFORE_MSK  				(0x00000001 << DELAYBEFORE_OFST)			//Not used in software
+#define DELAYAFTER_OFST  				(5)											//Not used in software
+#define DELAYAFTER_MSK  				(0x00000001 << DELAYAFTER_OFST)				//Not used in software
+#define STOPPED_OFST  					(15)
+#define STOPPED_MSK  					(0x00000001 << STOPPED_OFST)
+#define RUNMACHINE_BUSY_OFST  			(17)
+#define RUNMACHINE_BUSY_MSK  			(0x00000001 << RUNMACHINE_BUSY_OFST)
+
+
+/* Look at me register */
+#define LOOK_AT_ME_REG          		(0x03 << MEM_MAP_SHIFT)								//Not used in firmware or software
+
+/* System Status register */
+#define SYSTEM_STATUS_REG       		(0x04 << MEM_MAP_SHIFT)								//Not used in software
+
+#define DDR3_CAL_DONE_OFST				(0)											//Not used in software
+#define DDR3_CAL_DONE_MSK 				(0x00000001 << DDR3_CAL_DONE_OFST)			//Not used in software
+#define DDR3_CAL_FAIL_OFST				(1)											//Not used in software
+#define DDR3_CAL_FAIL_MSK 				(0x00000001 << DDR3_CAL_FAIL_OFST)			//Not used in software
+#define DDR3_INIT_DONE_OFST				(2)											//Not used in software
+#define DDR3_INIT_DONE_MSK 				(0x00000001 << DDR3_INIT_DONE_OFST)			//Not used in software
+#define RECONFIG_PLL_LCK_OFST			(3)											//Not used in software
+#define RECONFIG_PLL_LCK_MSK 			(0x00000001 << RECONFIG_PLL_LCK_OFST)		//Not used in software
+#define PLL_A_LCK_OFST					(4)											//Not used in software
+#define PLL_A_LCK_MSK 					(0x00000001 << PLL_A_LCK_OFST)				//Not used in software
+#define DD3_PLL_LCK_OFST				(5)											//Not used in software
+#define DD3_PLL_LCK_MSK 				(0x00000001 << DD3_PLL_LCK_OFST)			//Not used in software
+
+
+/* Module Control Board Serial Number Register */
+#define MOD_SERIAL_NUM_REG				(0x0A << MEM_MAP_SHIFT)								//Not used in software
+
+#define HARDWARE_SERIAL_NUM_OFST		(0)											//Not used in software
+#define HARDWARE_SERIAL_NUM_MSK			(0x000000FF << HARDWARE_SERIAL_NUM_OFST)	//Not used in software
+#define HARDWARE_VERSION_NUM_OFST		(16)										//Not used in software
+#define HARDWARE_VERSION_NUM_MSK		(0x0000003F << HARDWARE_VERSION_NUM_OFST)	//Not used in software
+
+
+/* API Version Register */
+#define API_VERSION_REG                 (0x0F << MEM_MAP_SHIFT)
+
+#define API_VERSION_OFST                (0)
+#define API_VERSION_MSK                 (0x00FFFFFF << API_VERSION_OFST)
+#define API_VERSION_DETECTOR_TYPE_OFST  (24)                                            //Not used in software
+#define API_VERSION_DETECTOR_TYPE_MSK   (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST)  //Not used in software
+
+/* Time from Start 64 bit register */
+#define TIME_FROM_START_LSB_REG   		(0x10 << MEM_MAP_SHIFT)
+#define TIME_FROM_START_MSB_REG   		(0x11 << MEM_MAP_SHIFT)
+
+/* Get Delay 64 bit register */
+#define GET_DELAY_LSB_REG     			(0x12 << MEM_MAP_SHIFT)						// different kind of delay
+#define GET_DELAY_MSB_REG     			(0x13 << MEM_MAP_SHIFT)						// different kind of delay
+
+/* Get Cycles 64 bit register */
+#define GET_CYCLES_LSB_REG    			(0x14 << MEM_MAP_SHIFT)
+#define GET_CYCLES_MSB_REG    			(0x15 << MEM_MAP_SHIFT)
+
+/* Get Frames 64 bit register */
+#define GET_FRAMES_LSB_REG   			(0x16 << MEM_MAP_SHIFT)
+#define GET_FRAMES_MSB_REG    			(0x17 << MEM_MAP_SHIFT)
+
+/* Get Period 64 bit register */
+#define GET_PERIOD_LSB_REG    			(0x18 << MEM_MAP_SHIFT)
+#define GET_PERIOD_MSB_REG    			(0x19 << MEM_MAP_SHIFT)
+
+/** Get Temperature Carlos, incorrectl as get gates */
+#define GET_TEMPERATURE_TMP112_REG		(0x1c << MEM_MAP_SHIFT)							// (after multiplying by 625) in 10ths of millidegrees of TMP112
+
+#define TEMPERATURE_POLARITY_BIT		(15)
+#define TEMPERATURE_POLARITY_MSK		(0x00000001 << TEMPERATURE_POLARITY_BIT)
+#define TEMPERATURE_VALUE_BIT			(0)
+#define TEMPERATURE_VALUE_MSK			(0x00007FFF << TEMPERATURE_VALUE_BIT)
+
+
+/* Get Frames from Start 64 bit register (frames from start Run Control) */
+#define FRAMES_FROM_START_PG_LSB_REG	(0x24 << MEM_MAP_SHIFT)
+#define FRAMES_FROM_START_PG_MSB_REG 	(0x25 << MEM_MAP_SHIFT)
+
+/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
+#define START_FRAME_TIME_LSB_REG		(0x26 << MEM_MAP_SHIFT)
+#define START_FRAME_TIME_MSB_REG 		(0x27 << MEM_MAP_SHIFT)
+
+/* SPI (Serial Peripheral Interface) Register */
+#define SPI_REG							(0x40 << MEM_MAP_SHIFT)
+
+#define DAC_SERIAL_DIGITAL_OUT_OFST		(0)
+#define DAC_SERIAL_DIGITAL_OUT_MSK		(0x00000001 << DAC_SERIAL_DIGITAL_OUT_OFST)
+#define DAC_SERIAL_CLK_OUT_OFST			(1)
+#define DAC_SERIAL_CLK_OUT_MSK			(0x00000001 << DAC_SERIAL_CLK_OUT_OFST)
+#define DAC_SERIAL_CS_OUT_OFST			(2)
+#define DAC_SERIAL_CS_OUT_MSK			(0x00000001 << DAC_SERIAL_CS_OUT_OFST)
+#define HV_SERIAL_DIGITAL_OUT_OFST		(8)
+#define HV_SERIAL_DIGITAL_OUT_MSK		(0x00000001 << HV_SERIAL_DIGITAL_OUT_OFST)
+#define HV_SERIAL_CLK_OUT_OFST			(9)
+#define HV_SERIAL_CLK_OUT_MSK			(0x00000001 << HV_SERIAL_CLK_OUT_OFST)
+#define HV_SERIAL_CS_OUT_OFST			(10)
+#define HV_SERIAL_CS_OUT_MSK			(0x00000001 << HV_SERIAL_CS_OUT_OFST)
+
+
+/* ADC SPI (Serial Peripheral Interface) Register */
+#define ADC_SPI_REG   					(0x41 << MEM_MAP_SHIFT)
+
+#define ADC_SERIAL_CLK_OUT_OFST			(0)
+#define ADC_SERIAL_CLK_OUT_MSK			(0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
+#define ADC_SERIAL_DATA_OUT_OFST		(1)
+#define ADC_SERIAL_DATA_OUT_MSK			(0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
+#define ADC_SERIAL_CS_OUT_OFST			(2)
+#define ADC_SERIAL_CS_OUT_MSK			(0x0000000F << ADC_SERIAL_CS_OUT_OFST)
+
+/* ADC offset Register */
+#define ADC_OFST_REG 					(0x42 << MEM_MAP_SHIFT)
+
+/* ADC Port Invert Register */
+#define ADC_PORT_INVERT_REG   			(0x43 << MEM_MAP_SHIFT)
+
+/* Receiver IP Address Register */
+#define RX_IP_REG    					(0x45 << MEM_MAP_SHIFT)
+
+/* UDP Port */
+#define UDP_PORT_REG    				(0x46 << MEM_MAP_SHIFT)
+
+#define UDP_PORT_RX_OFST				(0)
+#define UDP_PORT_RX_MSK					(0x0000FFFF << UDP_PORT_RX_OFST)
+#define UDP_PORT_TX_OFST				(16)
+#define UDP_PORT_TX_MSK					(0x0000FFFF << UDP_PORT_TX_OFST)
+
+/* Receiver Mac Address 64 bit Register */
+#define RX_MAC_LSB_REG					(0x47 << MEM_MAP_SHIFT)
+#define RX_MAC_MSB_REG					(0x48 << MEM_MAP_SHIFT)
+
+#define RX_MAC_LSB_OFST					(0)
+#define RX_MAC_LSB_MSK					(0xFFFFFFFF << RX_MAC_LSB_OFST)
+#define RX_MAC_MSB_OFST					(0)
+#define RX_MAC_MSB_MSK					(0x0000FFFF << RX_MAC_MSB_OFST)
+
+/* Detector/ Transmitter Mac Address 64 bit Register */
+#define TX_MAC_LSB_REG					(0x49 << MEM_MAP_SHIFT)
+#define TX_MAC_MSB_REG					(0x4A << MEM_MAP_SHIFT)
+
+#define TX_MAC_LSB_OFST					(0)
+#define TX_MAC_LSB_MSK					(0xFFFFFFFF << TX_MAC_LSB_OFST)
+#define TX_MAC_MSB_OFST					(0)
+#define TX_MAC_MSB_MSK					(0x0000FFFF << TX_MAC_MSB_OFST)
+
+/* Detector/ Transmitter IP Address Register */
+#define TX_IP_REG						(0x4B << MEM_MAP_SHIFT)
+
+/* Detector/ Transmitter IP Checksum Register */
+#define TX_IP_CHECKSUM_REG				(0x4C << MEM_MAP_SHIFT)
+
+#define TX_IP_CHECKSUM_OFST				(0)
+#define TX_IP_CHECKSUM_MSK				(0x0000FFFF << TX_IP_CHECKSUM_OFST)
+
+/* Configuration Register */
+#define CONFIG_REG            			(0x4D << MEM_MAP_SHIFT)
+
+#define CONFIG_OPERATION_MODE_OFST		(16)
+#define CONFIG_OPERATION_MODE_MSK		(0x00000001 << CONFIG_OPERATION_MODE_OFST)
+#define CONFIG_MODE_1_X_10GBE_VAL		((0x0 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
+#define CONFIG_MODE_2_X_10GBE_VAL		((0x1 << CONFIG_OPERATION_MODE_OFST) & CONFIG_OPERATION_MODE_MSK)
+#define CONFIG_READOUT_SPEED_OFST		(20)
+#define CONFIG_READOUT_SPEED_MSK		(0x00000003 << CONFIG_READOUT_SPEED_OFST)
+#define CONFIG_QUARTER_SPEED_10MHZ_VAL	((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_HALF_SPEED_20MHZ_VAL		((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_FULL_SPEED_40MHZ_VAL		((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_TDMA_OFST				(24)
+#define CONFIG_TDMA_MSK					(0x00000001 << CONFIG_TDMA_OFST)
+#define CONFIG_TDMA_DISABLE_VAL			((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
+#define CONFIG_TDMA_ENABLE_VAL			((0x1 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
+#define CONFIG_TDMA_TIMESLOT_OFST		(25)
+#define CONFIG_TDMA_TIMESLOT_MSK		(0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
+
+
+/* External Signal Register */
+#define EXT_SIGNAL_REG        			(0x4E << MEM_MAP_SHIFT)
+
+#define EXT_SIGNAL_OFST					(0)
+#define EXT_SIGNAL_MSK					(0x00000003 << EXT_SIGNAL_OFST)				//enabled when both bits high
+
+/* Control Register */
+#define CONTROL_REG           			(0x4F << MEM_MAP_SHIFT)
+
+#define CONTROL_START_ACQ_OFST       	(0)
+#define CONTROL_START_ACQ_MSK			(0x00000001 << CONTROL_START_ACQ_OFST)
+#define CONTROL_STOP_ACQ_OFST			(1)
+#define CONTROL_STOP_ACQ_MSK			(0x00000001 << CONTROL_STOP_ACQ_OFST)
+#define CONTROL_CORE_RST_OFST			(10)
+#define CONTROL_CORE_RST_MSK			(0x00000001 << CONTROL_CORE_RST_OFST)
+#define CONTROL_PERIPHERAL_RST_OFST		(11)										//DDR3 HMem Ctrlr, GBE, Temp
+#define CONTROL_PERIPHERAL_RST_MSK		(0x00000001 << CONTROL_PERIPHERAL_RST_OFST)	//DDR3 HMem Ctrlr, GBE, Temp
+#define CONTROL_DDR3_MEM_RST_OFST		(12)										//only PHY, not DDR3 PLL ,Not used in software
+#define CONTROL_DDR3_MEM_RST_MSK		(0x00000001 << CONTROL_DDR3_MEM_RST_OFST)	//only PHY, not DDR3 PLL ,Not used in software
+#define CONTROL_ACQ_FIFO_CLR_OFST		(14)
+#define CONTROL_ACQ_FIFO_CLR_MSK		(0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
+#define CONTROL_STORAGE_CELL_NUM_OFST   (16)
+#define CONTROL_STORAGE_CELL_NUM_MSK    (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
+
+/* Reconfiguratble PLL Paramater Register */
+#define PLL_PARAM_REG					(0x50 << MEM_MAP_SHIFT)
+
+/* Reconfiguratble PLL Control Regiser */
+#define PLL_CONTROL_REG					(0x51 << MEM_MAP_SHIFT)
+
+#define PLL_CTRL_RECONFIG_RST_OFST		(0)											//parameter reset
+#define PLL_CTRL_RECONFIG_RST_MSK		(0x00000001 << PLL_CTRL_RECONFIG_RST_OFST)	//parameter reset
+#define PLL_CTRL_WR_PARAMETER_OFST		(2)
+#define PLL_CTRL_WR_PARAMETER_MSK		(0x00000001 << PLL_CTRL_WR_PARAMETER_OFST)
+#define PLL_CTRL_RST_OFST				(3)
+#define PLL_CTRL_RST_MSK				(0x00000001 << PLL_CTRL_RST_OFST)
+#define PLL_CTRL_ADDR_OFST				(16)
+#define PLL_CTRL_ADDR_MSK				(0x0000003F << PLL_CTRL_ADDR_OFST)
+
+/* Sample Register (Obsolete) */
+#define SAMPLE_REG 						(0x59 << MEM_MAP_SHIFT)
+
+#define SAMPLE_ADC_SAMPLE_SEL_OFST		(0)
+#define SAMPLE_ADC_SAMPLE_SEL_MSK		(0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
+#define SAMPLE_ADC_SAMPLE_0_VAL			((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_1_VAL			((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_2_VAL			((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_3_VAL			((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_4_VAL			((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_5_VAL			((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_6_VAL			((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_7_VAL			((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+
+#define SAMPLE_ADC_DECMT_FACTOR_OFST	(4)
+#define SAMPLE_ADC_DECMT_FACTOR_MSK		(0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
+#define SAMPLE_ADC_DECMT_FACTOR_0_VAL	((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_1_VAL	((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_2_VAL	((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_3_VAL	((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_4_VAL	((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_5_VAL	((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_6_VAL	((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_7_VAL	((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+
+#define SAMPLE_DGTL_SAMPLE_SEL_OFST		(8)
+#define SAMPLE_DGTL_SAMPLE_SEL_MSK		(0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
+#define SAMPLE_DGTL_SAMPLE_0_VAL		((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_1_VAL		((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_2_VAL		((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_3_VAL		((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_4_VAL		((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_5_VAL		((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_6_VAL		((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_7_VAL		((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_8_VAL		((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_9_VAL		((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_10_VAL		((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_11_VAL		((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_12_VAL		((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_13_VAL		((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_14_VAL		((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_15_VAL		((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+
+#define SAMPLE_DGTL_DECMT_FACTOR_OFST	(12)
+#define SAMPLE_DGTL_DECMT_FACTOR_MSK	(0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
+#define SAMPLE_DECMT_FACTOR_1_VAL		((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DECMT_FACTOR_2_VAL		((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DECMT_FACTOR_4_VAL		((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+
+/** Vref Comp Mod Register */
+#define VREF_COMP_MOD_REG				(0x5C << MEM_MAP_SHIFT)
+
+#define VREF_COMP_MOD_OFST              (0)
+#define VREF_COMP_MOD_MSK               (0x00000FFF << VREF_COMP_MOD_OFST)
+#define VREF_COMP_MOD_ENABLE_OFST       (31)
+#define VREF_COMP_MOD_ENABLE_MSK        (0x00000FFF << VREF_COMP_MOD_ENABLE_OFST)
+
+
+/** DAQ Register */
+#define DAQ_REG							(0x5D << MEM_MAP_SHIFT)
+
+#define DAQ_SETTINGS_MSK                (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_HIGH_GAIN_OFST              (0)
+#define DAQ_HIGH_GAIN_MSK               (0x00000001 << DAQ_HIGH_GAIN_OFST)
+#define DAQ_FIX_GAIN_DYNMC_VAL          ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
+#define DAQ_FIX_GAIN_HIGHGAIN_VAL       ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
+#define DAQ_FIX_GAIN_OFST               (1)
+#define DAQ_FIX_GAIN_MSK                (0x00000003 << DAQ_FIX_GAIN_OFST)
+#define DAQ_FIX_GAIN_STG_1_VAL          ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
+#define DAQ_FIX_GAIN_STG_2_VAL          ((0x3 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
+#define DAQ_CMP_RST_OFST                (4)
+#define DAQ_CMP_RST_MSK                 (0x00000001 << DAQ_CMP_RST_OFST)
+#define DAQ_STRG_CELL_SLCT_OFST         (8)
+#define DAQ_STRG_CELL_SLCT_MSK          (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
+#define DAQ_FRCE_SWTCH_GAIN_OFST        (12)
+#define DAQ_FRCE_SWTCH_GAIN_MSK         (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
+#define DAQ_FRCE_GAIN_STG_1_VAL         ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_FRCE_GAIN_STG_2_VAL         ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_ELCTRN_CLLCTN_MDE_OFST      (14)
+#define DAQ_ELCTRN_CLLCTN_MDE_MSK       (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
+#define DAQ_G2_CNNT_OFST                (15)
+#define DAQ_G2_CNNT_MSK                 (0x00000001 << DAQ_G2_CNNT_OFST)
+#define DAQ_CRRNT_SRC_ENBL_OFST         (16)
+#define DAQ_CRRNT_SRC_ENBL_MSK          (0x00000001 << DAQ_CRRNT_SRC_ENBL_OFST)
+#define DAQ_CRRNT_SRC_CLMN_FIX_OFST     (17)
+#define DAQ_CRRNT_SRC_CLMN_FIX_MSK      (0x00000001 << DAQ_CRRNT_SRC_CLMN_FIX_OFST)
+#define DAQ_CRRNT_SRC_CLMN_SLCT_OFST    (20)
+#define DAQ_CRRNT_SRC_CLMN_SLCT_MSK     (0x0000003F << DAQ_CRRNT_SRC_CLMN_SLCT_OFST)
+
+/** Chip Power Register */
+#define CHIP_POWER_REG					(0x5E << MEM_MAP_SHIFT)
+
+#define CHIP_POWER_ENABLE_OFST			(0)
+#define CHIP_POWER_ENABLE_MSK			(0x00000001 << CHIP_POWER_ENABLE_OFST)
+#define CHIP_POWER_STATUS_OFST          (1)
+#define CHIP_POWER_STATUS_MSK           (0x00000001 << CHIP_POWER_STATUS_OFST)
+
+
+/** Temperature Control Register */
+#define TEMP_CTRL_REG                   (0x5F << MEM_MAP_SHIFT)
+
+#define TEMP_CTRL_PROTCT_THRSHLD_OFST   (0)
+#define TEMP_CTRL_PROTCT_THRSHLD_MSK    (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
+#define TEMP_CTRL_PROTCT_ENABLE_OFST    (16)
+#define TEMP_CTRL_PROTCT_ENABLE_MSK     (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
+#define TEMP_CTRL_OVR_TMP_EVNT_OFST     (31)
+#define TEMP_CTRL_OVR_TMP_EVNT_MSK      (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
+#define TEMP_CTRL_CLR_OVR_TMP_EVNT_VAL  ((0x1 << TEMP_CTRL_OVR_TMP_EVNT_OFST) & TEMP_CTRL_OVR_TMP_EVNT_MSK)
+
+
+/* Set Delay 64 bit register */
+#define SET_DELAY_LSB_REG     			(0x60 << MEM_MAP_SHIFT)					// different kind of delay
+#define SET_DELAY_MSB_REG     			(0x61 << MEM_MAP_SHIFT)					// different kind of delay
+
+/* Set Cycles 64 bit register */
+#define SET_CYCLES_LSB_REG    			(0x62 << MEM_MAP_SHIFT)
+#define SET_CYCLES_MSB_REG    			(0x63 << MEM_MAP_SHIFT)
+
+/* Set Frames 64 bit register */
+#define SET_FRAMES_LSB_REG   			(0x64 << MEM_MAP_SHIFT)
+#define SET_FRAMES_MSB_REG    			(0x65 << MEM_MAP_SHIFT)
+
+/* Set Period 64 bit register */
+#define SET_PERIOD_LSB_REG    			(0x66 << MEM_MAP_SHIFT)
+#define SET_PERIOD_MSB_REG    			(0x67 << MEM_MAP_SHIFT)
+
+/* Set Period 64 bit register */
+#define SET_EXPTIME_LSB_REG    			(0x68 << MEM_MAP_SHIFT)
+#define SET_EXPTIME_MSB_REG    			(0x69 << MEM_MAP_SHIFT)
+
+/* Trigger Delay 32 bit register */
+#define SET_TRIGGER_DELAY_LSB_REG       (0x70 << MEM_MAP_SHIFT)
+#define SET_TRIGGER_DELAY_MSB_REG       (0x71 << MEM_MAP_SHIFT)
+
+/* Module Coordinates Register 0 */
+#define COORD_0_REG						(0x7C << MEM_MAP_SHIFT)
+
+#define COORD_0_Y_OFST					(0)
+#define COORD_0_Y_MSK					(0x0000FFFF << COORD_0_Y_OFST)
+#define COORD_0_X_OFST					(16)
+#define COORD_0_X_MSK					(0x0000FFFF << COORD_0_X_OFST)
+
+/* Module Coordinates Register 1 */
+#define COORD_1_REG						(0x7D << MEM_MAP_SHIFT)
+
+#define COORD_0_Z_OFST					(0)
+#define COORD_0_Z_MSK					(0x0000FFFF << COORD_0_Z_OFST)
+
+/* ASIC Control Register */
+#define ASIC_CTRL_REG                   (0x7F << MEM_MAP_SHIFT)
+
+#define ASIC_CTRL_PRCHRG_TMR_OFST       (0)
+#define ASIC_CTRL_PRCHRG_TMR_MSK        (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
+#define ASIC_CTRL_PRCHRG_TMR_VAL        ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
+#define ASIC_CTRL_DS_TMR_OFST           (8)
+#define ASIC_CTRL_DS_TMR_MSK            (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
+#define ASIC_CTRL_DS_TMR_VAL            ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
+
+
+#endif  //REGISTERS_G_H
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

slsDetectorServers/jungfrauDetectorServer/ansi.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/ansi.h

slsDetectorServers/jungfrauDetectorServer/blackfin.h

@@ -0,0 +1 @@
+../slsDetectorServer/blackfin.h

slsDetectorServers/jungfrauDetectorServer/commonServerFunctions.h

@@ -0,0 +1 @@
+../slsDetectorServer/commonServerFunctions.h

slsDetectorServers/jungfrauDetectorServer/communication_funcs.c

@@ -0,0 +1 @@
+../../../slsSupportLib/include/communication_funcs.c

slsDetectorServers/jungfrauDetectorServer/communication_funcs.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/communication_funcs.h

slsDetectorServers/jungfrauDetectorServer/gitInfo.txt

@@ -0,0 +1,9 @@
+Path: slsDetectorPackage/slsDetectorSoftware/slsDetectorServers/jungfrauDetectorServer 
+URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git 
+Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git 
+Repsitory UUID: b9f97f42a6a369dfb5c484bffeaa7a417e9cbca1 
+Revision: 1 
+Branch: refactor 
+Last Changed Author: Dhanya_Thattil 
+Last Changed Rev: 4067 
+Last Changed Date: 2018-10-08 13:53:39.000000002 +0200 ./Makefile.virtual

slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrau.h

@@ -0,0 +1,6 @@
+#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
+#define GITREPUUID "b9f97f42a6a369dfb5c484bffeaa7a417e9cbca1"
+#define GITAUTH "Dhanya_Thattil"
+#define GITREV 0x4067
+#define GITDATE 0x20181008
+#define GITBRANCH "refactor"

slsDetectorServers/jungfrauDetectorServer/gitInfoJungfrauTmp.h

@@ -0,0 +1,6 @@
+#define GITURL ""
+#define GITREPUUID ""
+#define GITAUTH ""
+#define GITREV ""
+#define GITDATE ""
+#define GITBRANCH ""

slsDetectorServers/jungfrauDetectorServer/programfpga.h

@@ -0,0 +1 @@
+../slsDetectorServer/programfpga.h

slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorFunctionList.h

slsDetectorServers/jungfrauDetectorServer/slsDetectorServer.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer.c

slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h

@@ -0,0 +1,176 @@
+#ifndef SLSDETECTORSERVER_DEFS_H
+#define SLSDETECTORSERVER_DEFS_H
+
+#include "sls_detector_defs.h" 	//default dynamicgain in settings
+#include "RegisterDefs.h"
+#include <stdint.h>
+
+
+
+#define GOODBYE 					(-200)
+#define PROGRAMMING_MODE			(-200)
+#define MIN_REQRD_VRSN_T_RD_API     0x171220
+#define REQRD_FRMWR_VRSN            0x180615
+
+
+/* Struct Definitions */
+typedef struct ip_header_struct {
+	uint16_t     ip_len;
+	uint8_t      ip_tos;
+	uint8_t      ip_ihl:4 ,ip_ver:4;
+	uint16_t     ip_offset:13,ip_flag:3;
+	uint16_t     ip_ident;
+	uint16_t     ip_chksum;
+	uint8_t      ip_protocol;
+	uint8_t      ip_ttl;
+	uint32_t     ip_sourceip;
+	uint32_t     ip_destip;
+} ip_header;
+
+/* Enums */
+enum CLK_SPEED_INDEX		{FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
+enum ADCINDEX				{TEMP_FPGA, TEMP_ADC};
+enum DACINDEX				{VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
+#define DEFAULT_DAC_VALS   	{ 	1220,	/* VB_COMP */		\
+								3000,	/* VDD_PROT */		\
+								1053,	/* VIN_COM */		\
+								1450,	/* VREF_PRECH */	\
+								750,	/* VB_PIXBUF */		\
+								1000,	/* VB_DS */			\
+								480,	/* VREF_DS */		\
+								420		/* VREF_COMP */		\
+							};
+
+enum NETWORKINDEX           { TXN_FRAME };
+
+
+
+/* Hardware Definitions */
+#define NCHAN 						(256 * 256)
+#define NCHIP 						(8)
+#define NADC						(0)
+#define NDAC 						(8)
+#define NDAC_OLDBOARD				(16)
+#define DYNAMIC_RANGE				(16)
+#define NUM_BITS_PER_PIXEL			(DYNAMIC_RANGE / 8)
+#define DATA_BYTES					(NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
+#define IP_PACKETSIZE				(0x2052)
+#define CLK_RUN						(40)	/* MHz */
+#define CLK_SYNC					(20)	/* MHz */
+
+
+/** Default Parameters */
+#define DEFAULT_NUM_FRAMES			(100*1000*1000)
+#define DEFAULT_NUM_CYCLES			(1)
+#define DEFAULT_EXPTIME				(10*1000)		//ns
+#define DEFAULT_PERIOD				(2*1000*1000)	//ns
+#define DEFAULT_DELAY				(0)
+#define DEFAULT_HIGH_VOLTAGE		(0)
+#define DEFAULT_TIMING_MODE			(AUTO_TIMING)
+#define DEFAULT_SETTINGS			(DYNAMICGAIN)
+#define DEFAULT_TX_UDP_PORT			(0x7e9a)
+#define DEFAULT_TMP_THRSHLD         (65*1000) //milli degree Celsius
+#define DEFAULT_NUM_STRG_CLLS       (0)
+#define DEFAULT_STRG_CLL_STRT       (0xf)
+
+/* Defines in the Firmware */
+#define FIX_PATT_VAL    			(0xACDC2014)
+#define ADC_PORT_INVERT_VAL   		(0x453b2a9c)
+#define MAX_TIMESLOT_VAL            (0x1F)
+#define MAX_THRESHOLD_TEMP_VAL      (127999) //millidegrees
+#define MAX_STORAGE_CELL_VAL        (15) //0xF
+#define ACQ_TIME_MIN_CLOCK          (2)
+
+
+#define SAMPLE_ADC_HALF_SPEED	 	(SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL)	/* 0x1000 */
+#define SAMPLE_ADC_QUARTER_SPEED 	(SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL)	/* 0x2810 */
+#define CONFIG_HALF_SPEED			(CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
+#define CONFIG_QUARTER_SPEED		(CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_MODE_1_X_10GBE_VAL)
+#define ADC_OFST_HALF_SPEED_VAL		(0x1f) //(0x20)
+#define ADC_OFST_QUARTER_SPEED_VAL	(0x0f) //(0x0f)
+#define ADC_PHASE_HALF_SPEED 		(0x2D) //45
+#define ADC_PHASE_QUARTER_SPEED 	(0x2D) //45
+#define ADC_PORT_INVERT_VAL         (0x453b2a9c)
+
+/* Maybe not required for jungfrau */
+#define NTRIMBITS 					(6)
+#define NCOUNTBITS 					(24)
+#define NCHIPS_PER_ADC				(2)
+#define TRIM_DR 					(((int)pow(2,NTRIMBITS))-1)
+#define COUNT_DR 					(((int)pow(2,NCOUNTBITS))-1)
+#define ALLMOD 						(0xffff)
+#define ALLFIFO 					(0xffff)
+
+/* MSB & LSB DEFINES */
+#define MSB_OF_64_BIT_REG_OFST		(32)
+#define LSB_OF_64_BIT_REG_OFST		(0)
+#define BIT_32_MSK					(0xFFFFFFFF)
+
+/* LTC2620 DAC DEFINES */
+#define LTC2620_DAC_CMD_OFST		(20)
+#define LTC2620_DAC_CMD_MSK			(0x0000000F << LTC2620_DAC_CMD_OFST)
+#define LTC2620_DAC_ADDR_OFST		(16)
+#define LTC2620_DAC_ADDR_MSK		(0x0000000F << LTC2620_DAC_ADDR_OFST)
+#define LTC2620_DAC_DATA_OFST		(4)
+#define LTC2620_DAC_DATA_MSK		(0x00000FFF << LTC2620_DAC_DATA_OFST)
+
+#define LTC2620_DAC_CMD_WRITE		(0x00000000 << LTC2620_DAC_CMD_OFST)
+#define LTC2620_DAC_CMD_SET			(0x00000003 << LTC2620_DAC_CMD_OFST)
+#define LTC2620_DAC_CMD_POWER_DOWN	(0x00000004 << LTC2620_DAC_CMD_OFST)
+#define LTC2620_DAC_NUMBITS			(24)
+
+
+/* MAX1932 HV DEFINES */
+#define MAX1932_HV_NUMBITS			(8)
+#define MAX1932_HV_DATA_OFST		(0)
+#define MAX1932_HV_DATA_MSK			(0x000000FF << MAX1932_HV_DATA_OFST)
+
+
+
+/** PLL Reconfiguration Registers */
+//https://www.altera.com/documentation/mcn1424769382940.html
+#define PLL_MODE_REG 				(0x00)
+#define PLL_STATUS_REG 				(0x01)
+#define PLL_START_REG 				(0x02)
+#define PLL_N_COUNTER_REG 			(0x03)
+#define PLL_M_COUNTER_REG 			(0x04)
+#define PLL_C_COUNTER_REG 			(0x05)
+#define PLL_PHASE_SHIFT_REG			(0x06)
+
+#define PLL_SHIFT_NUM_SHIFTS_OFST	(0)
+#define PLL_SHIFT_NUM_SHIFTS_MSK	(0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
+
+#define PLL_SHIFT_CNT_SELECT_OFST	(16)
+#define PLL_SHIFT_CNT_SELECT_MSK	(0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
+#define PLL_SHIFT_CNT_SLCT_C0_VAL	((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C1_VAL	((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C2_VAL	((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C3_VAL	((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C4_VAL	((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C5_VAL	((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C6_VAL	((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C7_VAL	((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C8_VAL	((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C9_VAL	((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C10_VAL	((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C11_VAL	((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C12_VAL	((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C13_VAL	((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C14_VAL	((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C15_VAL	((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C16_VAL	((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+#define PLL_SHIFT_CNT_SLCT_C17_VAL	((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
+
+#define PLL_SHIFT_UP_DOWN_OFST		(21)
+#define PLL_SHIFT_UP_DOWN_MSK		(0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
+#define PLL_SHIFT_UP_DOWN_NEG_VAL	((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
+#define PLL_SHIFT_UP_DOWN_POS_VAL	((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
+
+#define PLL_K_COUNTER_REG 			(0x07)
+#define PLL_BANDWIDTH_REG 			(0x08)
+#define PLL_CHARGEPUMP_REG 			(0x09)
+#define PLL_VCO_DIV_REG 			(0x1c)
+#define PLL_MIF_REG 				(0x1f)
+
+
+#endif /* SLSDETECTORSERVER_DEFS_H */

slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.c

slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.h

slsDetectorServers/jungfrauDetectorServer/sls_detector_defs.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/sls_detector_defs.h

slsDetectorServers/jungfrauDetectorServer/sls_detector_funcs.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/sls_detector_funcs.h

slsDetectorServers/jungfrauDetectorServer/sls_receiver_defs.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/sls_receiver_defs.h

slsDetectorServers/jungfrauDetectorServer/sls_receiver_funcs.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/sls_receiver_funcs.h

slsDetectorServers/jungfrauDetectorServer/updateAPIVersion.sh

@@ -0,0 +1,7 @@
+SRCFILE=gitInfoJungfrau.h
+DSTFILE=versionAPI.h
+
+SRCPATTERN=GITDATE
+DSTPATTERN=APIJUNGFRAU
+
+awk -v a="$SRCFILE" -v b="$DSTFILE" -v c="$SRCPATTERN" -v d="$DSTPATTERN" 'FNR==NR&&$2==c{x=$3} NR!=FNR{if($2==d){$3="0x"substr(x,5)}print > b}' $SRCFILE $DSTFILE

slsDetectorServers/jungfrauDetectorServer/updateGitVersion.sh

@@ -0,0 +1,31 @@
+SERVER=jungfrauDetectorServer
+MAINDIR=slsDetectorPackage
+SPECDIR=slsDetectorSoftware/slsDetectorServers/$SERVER
+TMPFILE=gitInfoJungfrauTmp.h
+INCLFILE=gitInfoJungfrau.h
+
+
+#evaluate the variables
+EVALFILE=../../../evalVersionVariables.sh
+source $EVALFILE
+
+
+#get modified date
+#RDATE1='git log --pretty=format:"%ci" -1'
+RDATE1="find ../slsDetectorServer . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|bin|.git|updateGitVersion|.o' | head -n 1"
+RDATE=`eval $RDATE1`
+NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}') 
+NEWDATE=${NEWDATE/#/0x}
+
+
+#get old date from INCLFILE
+OLDDATE=$(more $INCLFILE | grep '#define GITDATE' | awk '{print $3}')
+
+
+#update INCLFILE if changes
+if [ "$OLDDATE" != "$NEWDATE" ]; then
+	echo Path: ${MAINDIR}/${SPECDIR}  $'\n'URL: ${GITREPO}  $'\n'Repository Root: ${GITREPO}  $'\n'Repsitory UUID: ${REPUID}  $'\n'Revision: ${FOLDERREV}  $'\n'Branch: ${BRANCH}  $'\n'Last Changed Author: ${AUTH1}_${AUTH2}  $'\n'Last Changed Rev: ${REV}  $'\n'Last Changed Date: ${RDATE} > gitInfo.txt 
+	cd ../../../
+	./genVersionHeader.sh $SPECDIR/gitInfo.txt $SPECDIR/$TMPFILE $SPECDIR/$INCLFILE 
+	cd $WD
+fi

slsDetectorServers/jungfrauDetectorServer/versionAPI.h

@@ -0,0 +1 @@
+../../../slsSupportLib/include/versionAPI.h