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2026-05-06 13:55:57 +00:00
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developer/commandline.html
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@@ -255,9 +255,8 @@
<div class="line">[Eiger] 1 is default. 0 deactivates readout and does not send data.</div>
</div>
</dd>
<dt id="term-adcclk-n_clk-in-MHz">adcclk [n_clk in MHz]<a class="headerlink" href="#term-adcclk-n_clk-in-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb] ADC clock frequency in MHz.</div>
<div class="line">[xilinx Ctb] ADC clock frequency in kHz.</div>
<dt id="term-adcclk-n_clk-optional-unit-Hz-default-kHz-MHz">adcclk [n_clk] [(optional unit) Hz(default)|kHz|MHz]<a class="headerlink" href="#term-adcclk-n_clk-optional-unit-Hz-default-kHz-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb][Xilinx Ctb] ADC clock frequency.</div>
</div>
</dd>
<dt id="term-adcenable-bitmask">adcenable [bitmask]<a class="headerlink" href="#term-adcenable-bitmask" title="Link to this term"></a></dt><dd><div class="line-block">
@@ -466,9 +465,8 @@
<div class="line">[Eiger] Enables or disables data streaming from left or/and right side of detector for 10 GbE mode. 1 (enabled) by default.</div>
</div>
</dd>
<dt id="term-dbitclk-n_clk-in-MHz">dbitclk [n_clk in MHz]<a class="headerlink" href="#term-dbitclk-n_clk-in-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb] Clock for latching the digital bits in MHz.</div>
<div class="line">[xilinx Ctb] Clock for latching the digital bits in kHz.</div>
<dt id="term-dbitclk-n_clk-optional-unit-Hz-default-kHz-MHz">dbitclk [n_clk] [(optional unit) Hz(default)|kHz|MHz]<a class="headerlink" href="#term-dbitclk-n_clk-optional-unit-Hz-default-kHz-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb][Xilinx Ctb] Clock for latching the digital bits.</div>
</div>
</dd>
<dt id="term-dbitphase-n_value-optional-deg">dbitphase [n_value] [(optional)deg]<a class="headerlink" href="#term-dbitphase-n_value-optional-deg" title="Link to this term"></a></dt><dd><div class="line-block">
@@ -1176,9 +1174,8 @@
<div class="line">Gui uses it to rearrange for complete image</div>
</div>
</dd>
<dt id="term-runclk-n_clk-in-MHz">runclk [n_clk in MHz]<a class="headerlink" href="#term-runclk-n_clk-in-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb] Run clock in MHz.</div>
<div class="line">[xilinx Ctb] Run clock in kHz.</div>
<dt id="term-runclk-n_clk-optional-unit-Hz-default-kHz-MHz">runclk [n_clk] [(optional unit) Hz(default)|kHz|MHz]<a class="headerlink" href="#term-runclk-n_clk-optional-unit-Hz-default-kHz-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb][Xilinx Ctb] Run clock frequency.</div>
</div>
</dd>
<dt id="term-runtime-optional-unit-ns-us-ms-s">runtime [(optional unit) ns|us|ms|s]<a class="headerlink" href="#term-runtime-optional-unit-ns-us-ms-s" title="Link to this term"></a></dt><dd><div class="line-block">
@@ -1495,8 +1492,8 @@
<div class="line">[Jungfrau][Moench] Enables or disables synchronization between modules. Sync mode requires at least one master configured. Also requires flatband cabling between master and slave with termination board.</div>
</div>
</dd>
<dt id="term-syncclk-n_clk-in-MHz">syncclk [n_clk in MHz]<a class="headerlink" href="#term-syncclk-n_clk-in-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb] Sync clock in MHz.</div>
<dt id="term-syncclk-n_clk-optional-unit-Hz-default-kHz-MHz">syncclk [n_clk] [(optional unit) Hz(default)|kHz|MHz]<a class="headerlink" href="#term-syncclk-n_clk-optional-unit-Hz-default-kHz-MHz" title="Link to this term"></a></dt><dd><div class="line-block">
<div class="line">[Ctb] Sync clock.</div>
</div>
</dd>
<dt id="term-temp_10ge-n_value">temp_10ge [n_value]<a class="headerlink" href="#term-temp_10ge-n_value" title="Link to this term"></a></dt><dd><div class="line-block">