CTB frequency rounding, CTB frequency measurement, CTB frequency units (#1423)

* round CTB clocks to next closest possible value, added freq measurement

* added time for firmware to measrue actual value after frequency change

* add check for backwards compatibility

* change CTB and XCTB clock values to MHz, TODO: units and validation errors

* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?

* do the same for dbit and adcclk

* added tolerance to exptime, fixed test

* update default values in server defs

* added virtual check in Altera_PLL, update testcases

* change python and pyctbgui to accept and return floating point MHz

* update help and comments

* Dev/ctb clocks fix (#1434)

* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)

* incorrect unit typo

* cmd generation and compiles

* default to MHz, removed space between units for consistency with timers, min and max checks for clks

* in python, but need to change the default to Hz again for clean code and intuition

* allow ints, doubles, implicit conversions

* dont allow raw ints, doubles and implicit conversions

* fixed tests

* added operators for Hz in python

* fix test for min clk for xilinx ctb

* fix test

* fix python tests

* fixed xilinx period and default clks

* test fix

* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb

* removing 3 clock cycle code from xilinx as well

* formatting

* loadpattern before 3 clk cycles code

* actualtime and measurement time to be implemented in 100ns already in fw

* fix tests

* pyzmq dependency forthe tests

* fixed pyctbgui for freq

* insert tolerance check again

* also added tolerance check for patwaittime

* formatting

* minor: rounding test

* removed Rep redundant in ToString for freq

* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary

* minor, and binaries

* minor, default clk vals are 0 but set up at detector setup

* get frequency only for that unit

* tolerance process

* missed in previous commit

* some more changes to exptime and validations

* ctb is probably done

* periodleft and delayleft

* fixed xilinx freq conv as well

* fixed m3 bug, binaries

* xilinx: setup also done in stop server so that the clk is not 0

* missed a test marker

* binaries in

* review fixes, simpler validation of timers in ctb and xilinx ctb

* typo fix

* format

* fix tests

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
This commit is contained in:
Martin Mueller
2026-05-06 15:52:13 +02:00
committed by GitHub
co-authored by muelle_m1 maliakal_d
parent bb1a73d718
commit 0837de2a5a
57 changed files with 2239 additions and 706 deletions
+17 -17
View File
@@ -1613,20 +1613,26 @@ class Detector {
/** [CTB] */
void setNumberOfAnalogSamples(int value, Positions pos = {});
/** [CTB] in MHz, [XCTB] in kHz */
Result<int> getADCClock(Positions pos = {}) const;
/** [CTB][XCTB] */
Result<defs::Hz> getADCClock(Positions pos = {}) const;
/** [CTB] in MHz, [XCTB] in kHz */
void setADCClock(int value_in_MHz, Positions pos = {});
/** [CTB][XCTB] */
void setADCClock(defs::Hz val, Positions pos = {});
/** [CTB] in MHz, [XCTB] in kHz */
Result<int> getRUNClock(Positions pos = {}) const;
/** [CTB][XCTB] */
Result<defs::Hz> getRUNClock(Positions pos = {}) const;
/** [CTB] in MHz, [XCTB] in kHz */
void setRUNClock(int value_in_MHz, Positions pos = {});
/** [CTB][XCTB] */
void setRUNClock(defs::Hz val, Positions pos = {});
/** [CTB] in MHZ */
Result<int> getSYNCClock(Positions pos = {}) const;
/** [CTB][XCTB] */
Result<defs::Hz> getDBITClock(Positions pos = {}) const;
/** [CTB][XCTB] */
void setDBITClock(defs::Hz val, Positions pos = {});
/** [CTB][XCTB] */
Result<defs::Hz> getSYNCClock(Positions pos = {}) const;
/** gets list of power enums */
std::vector<defs::powerIndex> getPowerList() const;
@@ -1721,12 +1727,6 @@ class Detector {
*/
void setReadoutMode(defs::readoutMode value, Positions pos = {});
/** [CTB] in MHz, [XCTB] in kHz */
Result<int> getDBITClock(Positions pos = {}) const;
/** [CTB] in MHz, [XCTB] in kHz */
void setDBITClock(int value_in_MHz, Positions pos = {});
/** [CTB] */
Result<int> getExternalSamplingSource(Positions pos = {}) const;
@@ -1934,7 +1934,7 @@ class Detector {
/** [CTB][Mythen3][Xilinx CTB] Gets the pattern file name including path of
* the last pattern uploaded. \n Returns an empty if nothing was uploaded or
* via a server default file*/
Result<std::string> getPatterFileName(Positions pos = {}) const;
Result<std::string> getPatternFileName(Positions pos = {}) const;
/** [CTB][Mythen3][Xilinx CTB] Loads ASCII pattern file directly to server
* (instead of executing line by line)*/
+3
View File
@@ -38,6 +38,7 @@ template <class T, class Allocator = std::allocator<T>> class Result {
template <typename V, typename = typename std::enable_if<
std::is_integral<V>::value &&
(std::is_same<T, time::ns>::value ||
std::is_same<T, defs::Hz>::value ||
std::is_same<T, bool>::value)>::type>
Result(const Result<V> &from) {
vec.reserve(from.size());
@@ -49,6 +50,7 @@ template <class T, class Allocator = std::allocator<T>> class Result {
template <typename V, typename = typename std::enable_if<
std::is_integral<V>::value &&
(std::is_same<T, time::ns>::value ||
std::is_same<T, defs::Hz>::value ||
std::is_same<T, bool>::value)>::type>
Result(Result<V> &from) {
vec.reserve(from.size());
@@ -60,6 +62,7 @@ template <class T, class Allocator = std::allocator<T>> class Result {
template <typename V, typename = typename std::enable_if<
std::is_integral<V>::value &&
(std::is_same<T, time::ns>::value ||
std::is_same<T, defs::Hz>::value ||
std::is_same<T, bool>::value)>::type>
Result(Result<V> &&from) {
vec.reserve(from.size());