CTB frequency rounding, CTB frequency measurement, CTB frequency units (#1423)

* round CTB clocks to next closest possible value, added freq measurement

* added time for firmware to measrue actual value after frequency change

* add check for backwards compatibility

* change CTB and XCTB clock values to MHz, TODO: units and validation errors

* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?

* do the same for dbit and adcclk

* added tolerance to exptime, fixed test

* update default values in server defs

* added virtual check in Altera_PLL, update testcases

* change python and pyctbgui to accept and return floating point MHz

* update help and comments

* Dev/ctb clocks fix (#1434)

* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)

* incorrect unit typo

* cmd generation and compiles

* default to MHz, removed space between units for consistency with timers, min and max checks for clks

* in python, but need to change the default to Hz again for clean code and intuition

* allow ints, doubles, implicit conversions

* dont allow raw ints, doubles and implicit conversions

* fixed tests

* added operators for Hz in python

* fix test for min clk for xilinx ctb

* fix test

* fix python tests

* fixed xilinx period and default clks

* test fix

* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb

* removing 3 clock cycle code from xilinx as well

* formatting

* loadpattern before 3 clk cycles code

* actualtime and measurement time to be implemented in 100ns already in fw

* fix tests

* pyzmq dependency forthe tests

* fixed pyctbgui for freq

* insert tolerance check again

* also added tolerance check for patwaittime

* formatting

* minor: rounding test

* removed Rep redundant in ToString for freq

* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary

* minor, and binaries

* minor, default clk vals are 0 but set up at detector setup

* get frequency only for that unit

* tolerance process

* missed in previous commit

* some more changes to exptime and validations

* ctb is probably done

* periodleft and delayleft

* fixed xilinx freq conv as well

* fixed m3 bug, binaries

* xilinx: setup also done in stop server so that the clk is not 0

* missed a test marker

* binaries in

* review fixes, simpler validation of timers in ctb and xilinx ctb

* typo fix

* format

* fix tests

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>

python/tests/test_det_api.py

@@ -396,6 +396,193 @@ def test_patternstart(session_simulator, request):
     Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
 
 
+
+@pytest.mark.detectorintegration
+def test_runclk(session_simulator, request):
+    """ Test using runclk for ctb and xilinx_ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    from slsdet import Hz, MHz, kHz
+
+    if det_type in ['ctb', 'xilinx_ctb']:
+        prev_runclk = d.getRUNClock()
+
+        d.runclk
+
+        # invalid value type
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = 5e6
+
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = 5 * 1000 * 1000
+
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = Hz(5e6)
+
+        d.runclk = MHz(15)
+        assert d.runclk.value == 15_000_000
+
+        d.runclk = MHz(14.5)
+        assert d.runclk.value == 14_500_000
+
+        d.runclk = kHz(15000.5)
+        assert d.runclk.value == 15_000_500
+
+        # invalid values from server
+        # max is 300MHz
+        with pytest.raises(Exception) as exc_info:
+            d.runclk = MHz(301)
+
+        # min is 2MHz for ctb and 10MHz for xilinx_ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.runclk = MHz(1)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.runclk = MHz(9)
+
+        c = MHz(2)
+        for rc in [5, 10, 15, 20]:
+            d.runclk = rc * c
+        assert d.runclk.value == 40_000_000
+
+        for i in range(len(d)):
+            d.setRUNClock(prev_runclk[i], [i])
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+@pytest.mark.detectorintegration
+def test_adcclk(session_simulator, request):
+    """ Test using adcclk for ctb and xilinx_ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    from slsdet import Hz, MHz, kHz
+
+    if det_type in ['ctb', 'xilinx_ctb']:
+        prev_adcclk = d.getADCClock()
+
+        d.adcclk
+
+        # invalid value type
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = 5e6
+
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = 5 * 1000 * 1000
+
+        with pytest.raises(Exception) as exc_info:
+            d.adcclk = Hz(5e6)
+
+        d.adcclk = MHz(15)
+        assert d.adcclk.value == 15_000_000
+
+        d.adcclk = MHz(14.5)
+        assert d.adcclk.value == 14_500_000
+
+        d.adcclk = kHz(15000.5)
+        assert d.adcclk.value == 15_000_500
+
+        # invalid values from server
+        # max is 300MHz for xilinx and 54 MHz for ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.adcclk = MHz(66)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.adcclk = MHz(301)
+
+        # min is 2MHz for ctb and 10MHz for xilinx_ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.adcclk = MHz(1)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.adcclk = MHz(9)
+
+        c = MHz(2)
+        for rc in [5, 10, 15, 20]:
+            d.adcclk = rc * c
+        assert d.adcclk.value == 40_000_000
+
+        for i in range(len(d)):
+            d.setADCClock(prev_adcclk[i], [i])
+         
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+@pytest.mark.detectorintegration
+def test_dbitclk(session_simulator, request):
+    """ Test using dbitclk for ctb and xilinx_ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    from slsdet import Hz, MHz, kHz
+
+    if det_type in ['ctb', 'xilinx_ctb']:
+        prev_dbitclk = d.getDBITClock()
+
+        d.dbitclk
+
+        # invalid value type
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = 5e6
+
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = 5 * 1000 * 1000
+
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = Hz(5e6)
+
+        d.dbitclk = MHz(15)
+        assert d.dbitclk.value == 15_000_000
+
+        d.dbitclk = MHz(14.5)
+        assert d.dbitclk.value == 14_500_000
+
+        d.dbitclk = kHz(15000.5)
+        assert d.dbitclk.value == 15_000_500
+
+        # invalid values from server
+        # max is 300MHz
+        with pytest.raises(Exception) as exc_info:
+            d.dbitclk = MHz(301)
+
+        # min is 2MHz for ctb and 10MHz for xilinx_ctb
+        if det_type == 'ctb':
+            with pytest.raises(Exception) as exc_info:
+                d.dbitclk = MHz(1)
+        else:
+            with pytest.raises(Exception) as exc_info:
+                d.dbitclk = MHz(9)
+
+        c = MHz(2)
+        for rc in [5, 10, 15, 20]:
+            d.dbitclk = rc * c
+        assert d.dbitclk.value == 40_000_000
+
+        for i in range(len(d)):
+            d.setDBITClock(prev_dbitclk[i], [i])
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+
+@pytest.mark.detectorintegration
+def test_syncclk(session_simulator, request):
+    """ Test using syncclk for ctb."""
+    det_type, num_interfaces, num_mods, d = session_simulator
+    assert d is not None
+
+    if det_type in ['ctb']:
+        d.syncclk
+
+    Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+
+
+
 @pytest.mark.detectorintegration
 def test_v_limit(session_simulator, request):
     """Test v_limit."""
@@ -715,3 +902,4 @@ def test_dac(session_simulator, request):
    
 
     Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
+