mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-21 19:30:03 +02:00
module id in udp header for virtual servers for debugging, formatting
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parent
182e5fdadb
commit
01d7831abf
@ -88,6 +88,7 @@ int eiger_virtual_read_n_rows = 256;
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int eiger_virtual_interrupt_subframe = 0;
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int eiger_virtual_left_datastream = 1;
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int eiger_virtual_right_datastream = 1;
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int eiger_virtual_module_id = 0;
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#endif
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int defaultDacValues[NDAC] = DEFAULT_DAC_VALS;
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@ -304,10 +305,9 @@ u_int32_t getDetectorIP() {
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void initControlServer() {
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LOG(logINFOBLUE, ("Configuring Control server\n"));
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if (!updateFlag && initError == OK) {
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#ifndef VIRTUAL
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int modid = getModuleIdInFile(&initError, initErrorMessage, ID_FILE);
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#else
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getModuleIdInFile(&initError, initErrorMessage, ID_FILE);
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#ifdef VIRTUAL
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eiger_virtual_module_id = modid;
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#endif
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if (initError == FAIL) {
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return;
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@ -2408,6 +2408,7 @@ void *start_timer(void *arg) {
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header->version = SLS_DETECTOR_HEADER_VERSION;
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header->frameNumber = frameNr + iframes;
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header->packetNumber = i;
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header->modId = eiger_virtual_module_id;
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header->row = row;
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header->column = colLeft;
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@ -2418,6 +2419,7 @@ void *start_timer(void *arg) {
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header->version = SLS_DETECTOR_HEADER_VERSION;
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header->frameNumber = frameNr + iframes;
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header->packetNumber = i;
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header->modId = eiger_virtual_module_id;
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header->row = row;
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header->column = colRight;
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if (eiger_virtual_quad_mode) {
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@ -41,6 +41,7 @@ char initErrorMessage[MAX_STR_LENGTH];
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#ifdef VIRTUAL
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pthread_t pthread_virtual_tid;
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int64_t virtual_currentFrameNumber = 2;
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int virtual_moduleid = 0;
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#endif
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enum detectorSettings thisSettings = UNINITIALIZED;
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@ -101,8 +102,9 @@ void basictests() {
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}
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// does check only if flag is 0 (by default), set by command line
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if ((!debugflag) && (!updateFlag) &&
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((validateKernelVersion(KERNEL_DATE_VRSN) == FAIL) || (checkType() == FAIL) ||
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(testFpga() == FAIL) || (testBus() == FAIL))) {
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((validateKernelVersion(KERNEL_DATE_VRSN) == FAIL) ||
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(checkType() == FAIL) || (testFpga() == FAIL) ||
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(testBus() == FAIL))) {
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sprintf(initErrorMessage,
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"Could not pass basic tests of FPGA and bus. Dangerous to "
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"continue. (Firmware version:0x%llx) \n",
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@ -480,6 +482,9 @@ void setupDetector() {
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// set module id in register
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int modid = getModuleIdInFile(&initError, initErrorMessage, ID_FILE);
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#ifdef VIRTUAL
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virtual_moduleid = modid;
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#endif
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if (initError == FAIL) {
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return;
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}
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@ -2083,40 +2088,56 @@ int setReadoutSpeed(int val) {
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case G2_108MHZ:
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LOG(logINFOBLUE, ("Setting readout speed to 108 MHz\n"));
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if (setClockDivider(READOUT_C0, SPEED_108_CLKDIV_0) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 0 to %d\n", SPEED_108_CLKDIV_0));
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to "
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"set readout clk 0 to %d\n",
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SPEED_108_CLKDIV_0));
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return FAIL;
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}
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if (setClockDivider(READOUT_C1, SPEED_108_CLKDIV_1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set readout clk 1 to %d\n", SPEED_108_CLKDIV_1));
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to "
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"set readout clk 1 to %d\n",
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SPEED_108_CLKDIV_1));
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return FAIL;
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}
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if (setPhase(READOUT_C1, SPEED_108_CLKPHASE_DEG_1, 1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set clk phase 1 %d deg\n", SPEED_108_CLKPHASE_DEG_1));
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to "
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"set clk phase 1 %d deg\n",
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SPEED_108_CLKPHASE_DEG_1));
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return FAIL;
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}
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setDBITPipeline(SPEED_144_DBIT_PIPELINE);
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if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
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LOG(logERROR, ("Could not set readout speed to 108 MHz. Failed to "
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"set dbitpipeline to %d \n",
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SPEED_144_DBIT_PIPELINE));
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return FAIL;
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}
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break;
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case G2_144MHZ:
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LOG(logINFOBLUE, ("Setting readout speed to 144 MHz\n"));
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if (setClockDivider(READOUT_C0, SPEED_144_CLKDIV_0) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 0 to %d\n", SPEED_144_CLKDIV_0));
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to "
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"set readout clk 0 to %d\n",
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SPEED_144_CLKDIV_0));
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return FAIL;
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}
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if (setClockDivider(READOUT_C1, SPEED_144_CLKDIV_1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set readout clk 1 to %d\n", SPEED_144_CLKDIV_1));
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to "
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"set readout clk 1 to %d\n",
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SPEED_144_CLKDIV_1));
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return FAIL;
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}
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if (setPhase(READOUT_C1, SPEED_144_CLKPHASE_DEG_1, 1) == FAIL) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set clk phase 1 %d deg\n", SPEED_144_CLKPHASE_DEG_1));
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to "
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"set clk phase 1 %d deg\n",
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SPEED_144_CLKPHASE_DEG_1));
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return FAIL;
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}
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setDBITPipeline(SPEED_144_DBIT_PIPELINE);
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if (getDBITPipeline() != SPEED_144_DBIT_PIPELINE) {
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to set dbitpipeline to %d \n", SPEED_144_DBIT_PIPELINE));
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LOG(logERROR, ("Could not set readout speed to 144 MHz. Failed to "
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"set dbitpipeline to %d \n",
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SPEED_144_DBIT_PIPELINE));
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return FAIL;
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}
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break;
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@ -3005,7 +3026,7 @@ void *start_timer(void *arg) {
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header->version = SLS_DETECTOR_HEADER_VERSION - 1;
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header->frameNumber = virtual_currentFrameNumber;
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header->packetNumber = 0;
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header->modId = 0;
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header->modId = virtual_moduleid;
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header->row = detPos[X];
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header->column = detPos[Y];
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// fill data
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@ -42,6 +42,7 @@ char initErrorMessage[MAX_STR_LENGTH];
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#ifdef VIRTUAL
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pthread_t pthread_virtual_tid;
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int64_t virtual_currentFrameNumber = 2;
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int virtual_moduleid = 0;
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#endif
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enum detectorSettings thisSettings = UNINITIALIZED;
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@ -448,6 +449,9 @@ void setupDetector() {
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// set module id in register
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int modid = getModuleIdInFile(&initError, initErrorMessage, ID_FILE);
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#ifdef VIRTUAL
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virtual_moduleid = modid;
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#endif
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if (initError == FAIL) {
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return;
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}
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@ -2282,7 +2286,7 @@ void *start_timer(void *arg) {
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header->version = SLS_DETECTOR_HEADER_VERSION - 1;
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header->frameNumber = virtual_currentFrameNumber;
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header->packetNumber = i;
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header->modId = 0;
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header->modId = virtual_moduleid;
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header->row = detPos[X];
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header->column = detPos[Y];
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