eiger receiver, receiving many packets at a time, with 16,8, 4 bitmode sort of working

This commit is contained in:
Maliakal Dhanya
2014-07-02 10:55:32 +02:00
parent b29879511b
commit 018b800117
20 changed files with 703 additions and 490 deletions

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@ -32,8 +32,9 @@ using namespace std;
#define COULDNOT_ENABLE_COMPRESSION 0x0080000000000000ULL
#define RECEIVER_DET_HOSTNAME_NOT_SET 0x0040000000000000ULL
#define RECEIVER_DET_HOSTTYPE_NOT_SET 0x0020000000000000ULL
#define DETECTOR_TEN_GIGA 0x0010000000000000ULL
// 0xFFFFFFFF00000000ULL
#define COULD_NOT_CONFIGURE_MAC 0x0000000000000001ULL
#define COULDNOT_SET_NETWORK_PARAMETER 0x0000000000000002ULL
@ -47,7 +48,9 @@ using namespace std;
#define RECEIVER_ACQ_PERIOD_NOT_SET 0x0000000000000200ULL
#define RECEIVER_FRAME_NUM_NOT_SET 0x0000000000000400ULL
#define RECEIVER_DYNAMIC_RANGE 0x0000000000000800ULL
#define RECEIVER_TEN_GIGA 0x0000000000001000ULL
// 0x00000000FFFFFFFFULL
/** @short class returning all error messages for error mask */
class errorDefs {

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@ -339,7 +339,8 @@ enum dacIndex {
E_rxb_lb, /**< eiger */
E_Vcp, /**< eiger */
E_Vcn, /**< eiger */
E_Vis /**< eiger */
E_Vis, /**< eiger */
IO_DELAY /**< eiger io delay */
};
/**
@ -413,7 +414,10 @@ enum readOutFlags {
PUMP_PROBE_MODE=0x8,/**<pump-probe mode */
BACKGROUND_CORRECTIONS=0x1000, /**<background corrections */
TOT_MODE=0x2000,/**<pump-probe mode */
CONTINOUS_RO=0x4000/**<pump-probe mode */
CONTINOUS_RO=0x4000,/**<pump-probe mode */
PARALLEL=0x10,/** <eiger parallel mode */
NONPARALLEL=0x20,/** <eiger serial mode */
SAFE=0x40/** <eiger safe mode */
};
/**
trimming modes

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@ -87,7 +87,10 @@ enum {
F_SET_SYNCHRONIZATION_MODE, /**< sets master/slave synchronization mode for multidetector structures */
F_READ_COUNTER_BLOCK, /**< reads the counter block memory for gotthard */
F_RESET_COUNTER_BLOCK, /**< resets the counter block memory for gotthard */
F_CALIBRATE_PEDESTAL /**< starts acquistion, calibrates pedestal and write back to fpga */
F_CALIBRATE_PEDESTAL, /**< starts acquistion, calibrates pedestal and write back to fpga */
F_ENABLE_TEN_GIGA /**< enable 10Gbe */
/* Always append functions hereafter!!! */