From c3e17ba05632309adcc896f858e52ecb07048a30 Mon Sep 17 00:00:00 2001
From: appel_c <christian.appel@psi.ch>
Date: Sat, 27 Jul 2024 17:41:56 +0200
Subject: [PATCH] fix: add write_access attribute to simulated readonly signal

---
 ophyd_devices/sim/sim_signals.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/ophyd_devices/sim/sim_signals.py b/ophyd_devices/sim/sim_signals.py
index 554ff2b..1de369b 100644
--- a/ophyd_devices/sim/sim_signals.py
+++ b/ophyd_devices/sim/sim_signals.py
@@ -1,3 +1,5 @@
+"""Module for signals of the ophyd_devices simulation."""
+
 import time
 
 import numpy as np
@@ -51,6 +53,7 @@ class SetableSignal(Signal):
         self.precision = precision
         self.sim = getattr(self.parent, "sim", None)
         self._update_sim_state(value)
+        self._metadata.update(write_access=True)
 
     def _update_sim_state(self, value: any) -> None:
         """Update the readback value."""
@@ -145,6 +148,7 @@ class ReadOnlySignal(Signal):
         self.sim = getattr(self.parent, "sim", None)
         if self.sim:
             self._init_sim_state()
+        self._metadata.update(write_access=False)
 
     def _init_sim_state(self) -> None:
         """Create the initial sim_state in the SimulatedData class of the parent device."""