add vs code
This commit is contained in:
Noah Piqué
@ -7,13 +7,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -38,6 +37,14 @@ extern "C" {
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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#if defined(STM32U5)
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#define CRYP_DATATYPE_32B CRYP_NO_SWAP
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#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
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#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
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#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
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#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
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#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
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#endif /* STM32U5 */
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/**
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* @}
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*/
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@ -206,6 +213,20 @@ extern "C" {
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* @{
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*/
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#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
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#if defined(STM32U5)
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#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
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#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
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#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
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#endif /* STM32U5 */
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/**
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* @}
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*/
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/** @defgroup CRC_Aliases CRC API aliases
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* @{
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*/
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#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
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#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
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/**
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* @}
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*/
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@ -235,11 +256,18 @@ extern "C" {
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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#if defined(STM32G4) || defined(STM32H7)
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#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32U5)
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#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
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#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
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#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
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#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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@ -469,15 +497,24 @@ extern "C" {
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#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
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#endif
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#if defined(STM32H7)
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#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
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#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
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#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
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#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
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#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
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#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
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#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
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#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
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#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
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#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
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#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
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#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
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#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
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#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
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#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
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#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
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#endif /* STM32H7 */
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#if defined(STM32U5)
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#define OB_USER_nRST_STOP OB_USER_NRST_STOP
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#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
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#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
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#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
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#define OB_USER_nBOOT0 OB_USER_NBOOT0
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#define OB_nBOOT0_RESET OB_NBOOT0_RESET
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#define OB_nBOOT0_SET OB_NBOOT0_SET
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#endif /* STM32U5 */
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/**
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* @}
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@ -520,6 +557,7 @@ extern "C" {
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#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
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#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
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#endif /* STM32G4 */
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/**
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* @}
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*/
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@ -594,12 +632,12 @@ extern "C" {
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#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
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#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
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#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
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#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
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#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
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#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
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#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
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#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
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#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
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#if defined(STM32L1)
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#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
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@ -615,6 +653,20 @@ extern "C" {
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#endif /* STM32F0 || STM32F3 || STM32F1 */
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#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
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#if defined(STM32U5)
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#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
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#endif /* STM32U5 */
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/**
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* @}
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*/
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/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#if defined(STM32U5)
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#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
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#endif /* STM32U5 */
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/**
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* @}
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*/
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@ -851,6 +903,21 @@ extern "C" {
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#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
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#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
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#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
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/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
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/**
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* @}
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*/
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#if defined(STM32U5)
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#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
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#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
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#define LPTIM_CHANNEL_ALL 0x00000000U
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#endif /* STM32U5 */
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/**
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* @}
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*/
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@ -1189,6 +1256,10 @@ extern "C" {
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#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
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#endif
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#if defined(STM32U5) || defined(STM32MP2)
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#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
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#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
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#endif
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/**
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* @}
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*/
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@ -1377,6 +1448,20 @@ extern "C" {
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*/
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#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
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#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
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|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
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|| defined(STM32H7) || defined(STM32U5)
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/** @defgroup DMA2D_Aliases DMA2D API Aliases
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* @{
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*/
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#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
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for compatibility with legacy code */
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/**
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* @}
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*/
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#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
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/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
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* @{
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*/
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@ -1395,6 +1480,29 @@ extern "C" {
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* @}
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*/
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/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
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* @{
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*/
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#if defined(STM32U5)
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#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
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#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
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#endif /* STM32U5 */
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/**
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* @}
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*/
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#if !defined(STM32F2)
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/** @defgroup HASH_alias HASH API alias
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* @{
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*/
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#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
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/**
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*
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* @}
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*/
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#endif /* STM32F2 */
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/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
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* @{
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*/
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@ -3327,6 +3435,31 @@ extern "C" {
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#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
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#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
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#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
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#if defined(STM32U5)
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#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
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#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
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#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
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#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
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#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
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#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
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#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
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#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
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#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
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#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
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#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
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#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
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#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
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#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
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#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
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#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
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#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
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#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
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#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
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#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
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#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
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#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
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#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
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#endif
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/**
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* @}
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@ -3344,7 +3477,7 @@ extern "C" {
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/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
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* @{
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*/
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#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
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#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
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#else
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#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
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#endif
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@ -3401,13 +3534,22 @@ extern "C" {
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* @}
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*/
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/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
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/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
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* @{
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*/
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#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
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#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
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#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
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#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
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#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
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#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
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#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
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#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
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#endif
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#if defined(STM32F4) || defined(STM32F2)
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#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
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#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
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@ -3750,5 +3892,4 @@ extern "C" {
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#endif /* STM32_HAL_LEGACY */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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